Semiconductor devices and methods of manufacture

US11342181B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11342181-B2
Application numberUS-202017071554-A
CountryUS
Kind codeB2
Filing dateOct 15, 2020
Priority dateMay 15, 2020
Publication dateMay 24, 2022
Grant dateMay 24, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming a stack of nanotubes, wherein individual nanotubes are aligned with adjacent nanotubes; depositing a supporting layer over the stack of nanotubes; removing the supporting layer, wherein the removing the supporting layer further removes at least one layer of nanotubes from the stack of nanotubes; and depositing a gate electrode over a remaining portion of the stack of nanotubes. 2. The method of claim 1 , wherein the forming the stack of nanotubes comprises filtering the individual nanotubes through a filter membrane. 3. The method of claim 2 , wherein the filter membrane has a first electrostatic field during the filtering the individual nanotubes. 4. The method of claim 3 , wherein the individual nanotubes are surrounded by a spacer material during the filtering the individual nanotubes, the spacer material having a second electrostatic field. 5. The method of claim 4 , wherein the stack of nanotubes has a nanotube density of about 500 nanotubes per micrometer. 6. The method of claim 4 , wherein the spacer material comprises a surfactant. 7. The method of claim 1 , further comprising, after the removing the supporting layer, removing a spacer material from around at least one nanotube within the remaining portion of the stack of nanotubes. 8. A method of manufacturing a semiconductor device, the method comprising: filtering a carbon nanotube solution through a filter membrane, the filter membrane having a electrostatic field, wherein during the filtering a first layer of carbon nanotubes, a second layer of carbon nanotubes, and a third layer of carbon nanotubes are deposited on the filter membrane; transferring the first layer of carbon nanotubes, the second layer of carbon nanotubes, and the third layer of carbon nanotubes to a dielectric layer over a substrate; removing the third layer of carbon nanotubes with a destructive removal process; removing the second layer of carbon nanotubes with a non-destructive removal process; and forming a gate electrode over the first layer of carbon nanotubes after the removing the second layer of carbon nanotubes. 9. The method of claim 8 , wherein the destructive removal process comprises a reactive ion etching process. 10. The method of claim 9 , wherein the non-destructive removal process comprises a mechanical exfoliation process. 11. The method of claim 10 , wherein the mechanical exfoliation process further comprising depositing a supporting layer over the second layer of carbon nanotubes, and wherein the mechanical exfoliation process removes both the supporting layer and the second layer of carbon nanotubes. 12. The method of claim 11 , wherein the mechanical exfoliation process further removes carbon nanotubes damaged during the destructive removal process. 13. The method of claim 8 , further comprising removing a spacer material from carbon nanotubes within the first layer of carbon nanotubes. 14. The method of claim 13 , wherein the first layer of carbon nanotubes has a density of about 500 nanotubes per micrometers. 15. A method of manufacturing a semiconductor device, the method comprising: receiving a solution, the solution comprising carbon nanotubes; aligning the carbon nanotubes using a first electrostatic field into a stack of aligned carbon nanotubes; placing the stack of aligned carbon nanotubes onto a dielectric material; thinning the stack of aligned carbon nanotubes a first time with a first process; thinning the stack of aligned carbon nanotubes a second time with a second process different from the first process; and depositing a source/drain contact in electrical connection with the stack of aligned carbon nanotubes after the thinning the stack of aligned carbon nanotubes the second time. 16. The method of claim 15 , wherein the first process is an etching process. 17. The method of claim 16 , wherein the second process is an exfoliation process. 18. The method of claim 15 , wherein the first electrostatic field is generated by a material located on a filter membrane. 19. The method of claim 18 , wherein the carbon nanotubes are surrounded by a spacer material during the aligning the carbon nanotubes, the spacer material generating a second electrostatic field. 20. The method of claim 15 , wherein after the thinning the stack of aligned carbon nanotubes the second time a thickness of the stack of aligned carbon nanotubes is less than 2 nm.

Assignees

Inventors

Classifications

  • Nanotubes · CPC title

  • Thermal treatment, e.g. annealing in the presence of a solvent vapour · CPC title

  • Disposition of the gate electrodes, e.g. buried gates · CPC title

  • Manufacture or treatment · CPC title

  • Diamond · CPC title

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Frequently asked questions

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What does patent US11342181B2 cover?
A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification B01D67/00416. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue May 24 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).