Driver leakage control

Patent metadata

Field	Value
Publication number	US-11342014-B1
Application number	US-202117306311-A
Country	US
Kind code	B1
Filing date	May 3, 2021
Priority date	May 3, 2021
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

Embodiments herein relate to column select circuitry of a memory device. Specifically, the column select circuitry includes a pre-header circuit coupled to a pre-driver circuit. The pre-header circuit is configured to couple a gate of a transistor of a main column select driver circuit of the column select circuitry to a first voltage supply during operation and a second voltage supply when in a standby state. A voltage of the second voltage supply is greater than a voltage of the first voltage supply. The voltage of the second power supply applied to the gate of the transistor of the main column select driver circuit reduces current leakage through the transistor and enables a reduction in a size of the column select circuitry.

First claim

What is claimed is:

1. A select circuit comprising:
an input configured to receive a first signal;
a first node configured to enable an output of the select circuit;
a second node configured to control a voltage level of the first node;
a decoder circuit configured to receive a second signal and a third signal and configured to selectively couple the second node to a first voltage or a second voltage based on the second signal and the third signal;
a main driver circuit configured to provide the output of the select circuit; and
a pre-header circuit configured to selectively couple the first node to the first voltage or a third voltage based on a voltage level of the second node, wherein a voltage level of the first node is configured to control a leakage current in the main driver circuit.

2. The select circuit of claim 1 , comprising a first transistor configured to selectively couple the first node to the pre-header circuit based on the first signal.

3. The select circuit of claim 1 , comprising a second transistor configured to selectively couple the first node to the decoder circuit based on the first signal.

4. The select circuit of claim 1 , the decoder circuit comprising a first transistor and a second transistor configured to receive the second signal or the third signal, wherein the first transistor is configured to selectively couple the second node to the first voltage and the second transistor is configured to selectively couple the second node to the second voltage.

5. The select circuit of claim 1 , wherein the third voltage is greater than the first voltage and the second voltage.

6. The select circuit of claim 1 , wherein the main driver circuit comprises a first transistor configured to selectively couple the output to the first voltage based on the voltage level of the first node and a second transistor configured to selectively couple the output to the second voltage based on the voltage level of the first node.

7. The select circuit of claim 6 , wherein the pre-header circuit comprises a third transistor configured to selectively couple the first node to the first voltage and a fourth transistor configured to selectively couple the first node to the third voltage, wherein a size of the third transistor and the fourth transistor is less than 1.5 microns (μm).

8. The select circuit of claim 7 , wherein a size of the first transistor is about 10.5 microns (μm).

9. The select circuit of claim 7 , wherein the pre-header circuit comprises an inverter coupled to the second node and the fourth transistor.

10. A memory device comprising:
a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each memory cell of the plurality of memory cells is configured to store a data bit;
row select circuitry configured to identify a memory cell row of the plurality of memory cell rows corresponding to an address of a particular memory cell;
column select circuitry configured to identify a memory cell column of the plurality of memory cell columns corresponding to the address of the particular memory cell, the column select circuitry comprising:
an input configured to receive a first signal;
a first node configured to enable an output of the column select circuit;
a second node configured to control a voltage level of the first node;
a decoder circuit configured to receive a second signal and a third signal and configured to selectively couple the second node to a first voltage or a second voltage based on the second signal and the third signal;
a main driver circuit configured to provide the output of the column select circuit; and
a pre-header circuit configured to selectively couple the first node to the first voltage or a third voltage based on a voltage level of the second node.

11. The memory device of claim 10 , the decoder circuit comprising a first transistor and a second transistor configured to receive the second signal or the third signal, wherein the first transistor is configured to selectively couple the second node to the first voltage and the second transistor is configured to selectively couple the second node to the second voltage.

12. The memory device of claim 11 , the main driver circuit comprising a third transistor configured to selectively couple the output to the first voltage and a fourth transistor configured to selectively couple the output to the second voltage.

13. The memory device of claim 12 , the pre-header circuit comprising a fifth transistor configured to selectively couple the first node to the first voltage, an inverter coupled to the second node, and a sixth transistor coupled to the inverter and configured to selectively couple the first node to the first voltage or the third voltage based on the voltage level of the second node.

14. The memory device of claim 10 , comprising a pre-driver circuit including a first transistor configured to selectively couple the first node to the second node based on the first signal and a second transistor configured to selectively couple the first node to the pre-header circuit based on the first signal.

15. The memory device of claim 12 , wherein the voltage level of the first node is configured to mitigate a leakage current through the third transistor when the column select circuitry is in a standby state.

16. A memory system comprising:
an input configured to receive a first signal;
a first node configured to enable an output of a select circuit;
a second node configured to control a voltage level of the first node;
a decoder circuit configured to receive a second signal and a third signal and configured to selectively couple the second node to a first voltage or a second voltage based on the second signal and the third signal;
a main driver circuit configured to provide the output of the select circuit;
a pre-driver circuit configured to receive the first signal and configured to selectively provide a voltage level to the first node; and
a pre-footer circuit configured to selectively couple the first node to the first voltage or a third voltage based on a voltage level of the second node, wherein a voltage level of the first node is configured to control a leakage current in the main driver circuit.

17. The memory system of claim 16 , the decoder circuit comprising a first transistor and a second transistor configured to receive the second signal or the third signal, wherein the first transistor is configured to selectively couple the second node to the first voltage and the second transistor is configured to selectively couple the second node to the second voltage.

18. The memory system of claim 16 , wherein the third voltage is less than the first voltage and the second voltage.

19. The memory system of claim 16 , the pre-footer circuit comprising a fifth transistor configured to selectively couple the first node to the first voltage, an inverter coupled to the second node, and a sixth transistor coupled to the inverter and configured to selectively couple the first node to the first voltage or the third voltage based on the voltage level of the second node.

20. The memory system of claim 19 , comprising a seventh transistor configured to selectively couple the output to the first voltage based on the voltage level of the first node, wherein a size of the seventh transistor is about 10.5 microns (μm), and wherein a size of the fifth transistor and the sixth transistor is less than 1.5 microns (μm).

Assignees

• Micron Technology Inc

Inventors

• Ingalls Charles L

Classifications

• G11C8/10 Primary

  Decoders · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title