Compute-in-memory (CIM) binary multiplier

Patent metadata

Field	Value
Publication number	US-11340867-B2
Application number	US-202016807562-A
Country	US
Kind code	B2
Filing date	Mar 3, 2020
Priority date	Mar 3, 2020
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.

First claim

What is claimed is:

1. A circuit for binary multiplication, comprising:
a memory cell having at least one of a bit-line or a complementary bit-line;
a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and
an adder coupled to the computation circuit, wherein the computation circuit comprises:
a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell,
a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS transistor and the first PMOS transistor being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node, and
an enable circuit comprising a second NMOS transistor coupled between the adder and the drains of the first NMOS transistor and the first PMOS transistor, a gate of the second NMOS transistor being coupled to an enable node.

2. The circuit of claim 1 , wherein gates of the first NMOS transistor and the first PMOS transistor are coupled to the bit-line.

3. The circuit of claim 1 , wherein gates of the first NMOS transistor and the first PMOS transistor are coupled to the complementary bit-line.

4. The circuit of claim 1 , wherein the computation circuit is configured to perform an AND operation.

5. The circuit of claim 1 , wherein the enable circuit further comprises:
a second PMOS transistor having a source coupled to a drain of the second NMOS transistor and a drain coupled to a source of the second NMOS transistor, a gate of the second PMOS transistor being coupled to a complementary enable node.

6. The circuit of claim 1 , wherein the memory cell is one of a plurality of memory cells of a static random-access memory (SRAM).

7. The circuit of claim 1 , wherein the computation circuit further comprises a first inverter coupled between the adder and the drains of the first NMOS transistor and the first PMOS transistor.

8. The circuit of claim 7 , wherein gates of the first NMOS transistor and the first PMOS transistor are coupled to the bit-line, and wherein the computation circuit further comprises a second inverter between the adder and the first inverter.

9. The circuit of claim 1 , wherein the computation input node comprises an output of a register.

10. A method for binary computation, comprising:
reading a first computation parameter in a memory cell having at least one of a bit-line or a complementary bit-line;
providing a second computation parameter to a computation input node of a computation circuit;
computing a logical operation of the first computation parameter and the second computation parameter via the computation circuit coupled to the bit-line or the complementary bit-line, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node;
enabling the computation circuit via an enable signal provided to an enable node of an enable circuit, wherein the enable circuit comprises a second NMOS transistor coupled between the adder and the drains of the first NMOS transistor and the first PMOS transistor, a gate of the second NMOS transistor being coupled to the enable node; and
performing, via an adder, an add operation based on a signal at drains of the first NMOS transistor and the first PMOS transistor.

11. The method of claim 10 , wherein the logical operation comprises an AND operation.

12. The method of claim 10 , wherein gates of the first NMOS transistor and the first PMOS transistor are coupled to the bit-line.

13. The method of claim 10 , wherein gates of the first NMOS transistor and the first PMOS transistor are coupled to the complementary bit-line.

14. The method of claim 10 , wherein the computation circuit is further enabled via a complementary enable signal provided to a complementary enable node of the enable circuit, the enable circuit further having:
a second PMOS transistor having a source coupled to a drain of the second NMOS transistor and a drain coupled to a source of the second NMOS transistor, a gate of the second PMOS transistor being coupled to the complementary enable node.

15. The method of claim 10 , wherein the computation input node comprises an output of a register.

16. The method of claim 10 , wherein the computation circuit further comprises a first inverter coupled between the adder and the drains of the first NMOS transistor and the first PMOS transistor.

Assignees

• Qualcomm Inc

Inventors

• Li Xia
• Wang Zhongze
• Chidambaram Periannan

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/084

  Backpropagation, e.g. using gradient descent · CPC title

• H04N19/42 Primary

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title