Quenching of a SPAD

Patent metadata

Field	Value
Publication number	US-11336853-B2
Application number	US-202017063192-A
Country	US
Kind code	B2
Filing date	Oct 5, 2020
Priority date	Oct 7, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.

First claim

The invention claimed is:

1. A device, comprising:
a photodiode having a first terminal and a second terminal;
a resistor coupled between the first terminal of the photodiode and a first rail configured to receive a high supply potential;
a switch coupled between the second terminal of the photodiode and a second rail configured to receive a reference potential;
a read circuit configured to provide a pulse when the photodiode enters into avalanche; and
a control circuit configured to control an opening of the switch in response to a beginning of said pulse and to control a closing of the switch in response to an end of said pulse,
wherein the control circuit includes a logic gate having an input configured to receive said pulse and an output configured to provide a control signal to the switch,
wherein the control circuit is further configured to control a slope of the control signal as a function of a value of a slope adjustment potential, during a switching of the control signal causing a closing of the switch,
wherein the control circuit includes a MOS transistor connected between a supply terminal of the control circuit and a first supply terminal of the logic gate of the control circuit, a gate of the MOS transistor being configured to receive the slope adjustment potential.

2. The device according to claim 1 , wherein the switch is a MOS transistor.

3. The device according to claim 1 , configured to interrupt a conductive path coupling the second terminal of the photodiode to the second rail via the switch for as long as a deactivation signal for deactivating the device is in a first state.

4. The device according to claim 3 , further comprising:
an additional switch connected in series with said switch between the second terminal of the photodiode and the second rail, the additional switch configured to deactivate the device in response to the deactivation signal.

5. The device according to claim 3 , wherein the input of the logic gate of the control circuit is configured to receive the deactivation signal for deactivating the device.

6. The device according to claim 1 , wherein the control circuit is further configured to keep the switch closed for as long as a deactivation signal for deactivating the control circuit is in a first state, the logic gate of the control circuit including an input configured to receive the deactivation signal for deactivating the control circuit.

7. The device according to claim 1 , wherein the gate of the MOS transistor is configured to receive a deactivation signal for deactivating the control circuit.

8. The device according to claim 1 , further comprising a capacitive bridge divider connected between the first terminal of the photodiode and the second rail, an input terminal of the read circuit being connected to an intermediate node of the capacitive divider bridge.

9. The device according to claim 8 , wherein the read circuit is further configured to modify a duration of the pulse as a function of a value of a pulse-duration adjustment potential.

10. The device according to claim 9 , wherein the read circuit includes a MOS transistor connected between a supply terminal of the read circuit and the intermediate node, a gate of the MOS transistor being configured to receive the pulse-duration adjustment potential.

11. The device according to claim 8 , wherein the read circuit includes a logic gate having an input terminal coupled to the intermediate node, and an output terminal configured to provide said pulse.

12. The device according to claim 1 , wherein the read circuit and the control circuit are each connected between the second rail and a third rail configured to receive a low supply potential.

13. The device according to claim 1 , further comprising a potential-limiting circuit configured to limit a maximum level of potential on the second terminal of the photodiode, the potential-limiting circuit including an additional photodiode connected between the second terminal of said photodiode and a node configured to receive an intermediate supply potential.

14. The device according to claim 1 , further comprising a capacitor connected between the second terminal of said photodiode and the second rail.

15. An image sensor, comprising:
a plurality of devices arranged in a matrix of pixels of the image sensor, each of the plurality of devices including:
a photodiode having a first terminal and a second terminal;
a resistor coupled between the first terminal of the photodiode and a first rail configured to receive a high supply potential;
a switch coupled between the second terminal of the photodiode and a second rail configured to receive a reference potential;
a read circuit configured to provide a pulse when the photodiode enters into avalanche; and
a control circuit configured to control an opening of the switch in response to a beginning of said pulse and to control a closing of the switch in response to an end of said pulse,
wherein the control circuit includes a logic gate having an input configured to receive said pulse and an output configured to provide a control signal to the switch, and a MOS transistor connected between a supply terminal of the logic gate of the control circuit and the second rail, a gate of the MOS transistor being configured to receive a deactivation signal for deactivating the control circuit.

16. The image sensor of claim 15 , wherein the read circuit and the control circuit are each connected between the second rail and a third rail configured to receive a low supply potential.

17. The image sensor of claim 15 , wherein each of the plurality of devices is configured to interrupt a conductive path coupling the second terminal of the photodiode to the second rail via the switch for as long as a deactivation signal for deactivating the device is in a first state.

18. The image sensor of claim 17 , wherein each of the plurality of devices further includes:
an additional switch connected in series with said switch between the second terminal of the photodiode and the second rail, the additional switch configured to deactivate the device in response to the deactivation signal.

19. The image sensor of claim 17 , wherein input of the logic gate of the control circuit is configured to receive the deactivation signal for deactivating the device.

20. The image sensor of claim 15 , wherein the control circuit is further configured to keep the switch closed for as long as a deactivation signal for deactivating the control circuit is in a first state, the logic gate of the control circuit including an input configured to receive the deactivation signal for deactivating the control circuit.

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Res & Dev Ltd

Inventors

• Bianchi Raul Andres
• Vignetti Matteo Maria
• Rae Bruce

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/773

  comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] · CPC title

• H10F77/959 Primary

  for devices working in avalanche mode · CPC title

• G01J2001/4466

  Avalanche · CPC title

• G01J1/46

  using a capacitor · CPC title