Quantum dot devices with overlapping gates

Patent metadata

Field	Value
Publication number	US-11335778-B2
Application number	US-201816018751-A
Country	US
Kind code	B2
Filing date	Jun 26, 2018
Priority date	Jun 26, 2018
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack;
a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and
a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

2. The quantum dot device of claim 1 , wherein the first gate dielectric has a U-shaped cross-section.

3. The quantum dot device of claim 1 , wherein the first gate is at least partially between a portion of the second gate dielectric and the quantum well stack.

4. The quantum dot device of claim 1 , wherein the first gate dielectric is at least partially between a portion of the second gate metal and the quantum well stack.

5. The quantum dot device of claim 1 , wherein the first gate metal is at least partially between a portion of the second gate metal and the quantum well stack.

6. The quantum dot device of claim 1 , wherein the first gate dielectric and the second gate dielectric have different material structures.

7. The quantum dot device of claim 1 , wherein the first gate metal and the second gate metal have different material structures.

8. The quantum dot device of claim 1 , further comprising:
a dielectric cap at least partially between the first gate metal and the second gate.

9. The quantum dot device of claim 8 , wherein side surfaces of the dielectric cap contact the first gate dielectric.

10. The quantum dot device of claim 8 , wherein the second gate dielectric contacts the dielectric cap.

11. The quantum dot device of claim 1 , further comprising:
at least one dielectric spacer above the first gate.

12. The quantum dot device of claim 1 , further comprising:
a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

13. The quantum dot device of claim 1 , wherein first gate metal has a height that is different from a height of the second gate metal.

14. The quantum dot device of claim 1 , further comprising:
doped regions in the quantum well stack.

15. A method of operating a quantum dot device, comprising:
providing electrical signals to a first gate above a quantum well stack as part of causing a first quantum well to form in a quantum well layer in the quantum well stack;
providing electrical signals to a second gate above the quantum well stack as part of causing a second quantum well to form in the quantum well layer in the quantum well stack; and
providing electrical signals to a third gate above the quantum well stack to (1) cause a third quantum well to form in the quantum well layer in the quantum well stack or (2) provide a potential barrier between the first quantum well and the second quantum well;
wherein the first gate includes a first gate metal and a first gate dielectric, the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

16. The method of claim 15 , wherein at least two of the first, second, or third gate have a gate wall between them, the gate wall includes a first dielectric material and a second dielectric material, and the first dielectric material is at least partially between the second dielectric material and the quantum well stack.

17. A method of manufacturing a quantum dot device, comprising:
forming a quantum well stack;
forming a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and
forming a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

18. The method of claim 17 , wherein forming the second gate includes:
forming a patterned insulating material over the first gate, wherein an opening in the patterned insulating material exposes a portion of the quantum well stack adjacent to the first gate;
forming a conformal gate dielectric on side surfaces of the opening; and
depositing a gate metal on the conformal gate dielectric.

19. The method of claim 18 , further comprising:
recessing the gate metal; and
forming dielectric caps on the recessed gate metal.

20. The method of claim 17 , wherein forming the first gate includes:
depositing a dummy material above the quantum well stack;
patterning the dummy material into dummy gates;
depositing a barrier layer conformally on the dummy gates; and
forming spacers on the barrier layer on sidewalls of the dummy gates.

21. The method of claim 20 , wherein the dummy material is a first dummy material, and forming the first gate further includes:
depositing a second dummy material between the spacers;
after depositing the second dummy material, removing the first dummy material;
after removing the first dummy material, conformally depositing a gate dielectric; and
after conformally depositing the gate dielectric, depositing a gate metal.

22. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes at least a quantum well stack, a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric, and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to at least one of the first gate and the second gate.

23. The quantum computing device of claim 22 , further comprising:
a package substrate, wherein the quantum processing device is coupled to the package substrate.

24. The quantum computing device of claim 22 , further comprising:
a refrigeration unit.

25. The quantum computing device of claim 22 , wherein at least one of the first gate and the second gate is on a fin or in a trench.

Assignees

• Intel Corp

Inventors

• Thomas Nicole K
• Pillarisetty Ravi
• Singh Kanwaljit
• George Hubert C
• Michalak David J
• Lampert Lester
• Yoscovits Zachary R
• Caudillo Roman
• Roberts Jeanette M
• Clarke James S

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title