Array substrate, display apparatus, and method of fabricating array substrate

Patent metadata

Field	Value
Publication number	US-11335712-B2
Application number	US-201916755652-A
Country	US
Kind code	B2
Filing date	May 13, 2019
Priority date	May 13, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

An array substrate is provided. The array substrate includes a base substrate; a first bonding pad layer including a plurality of first bonding pads on a first side of the base substrate; a second bonding pad layer including a plurality of second bonding pads on a second side of the base substrate, wherein the second side is opposite to the first side; and a plurality of signal lines on a side of the second bonding pad layer away from the base substrate. A respective one of the plurality of second bonding pads extends through the base substrate to electrically connect to a respective one of the plurality of first bonding pads. The respective one of the plurality of first bonding pads includes a protruding portion protruding away from the first side of the base substrate along a direction from the second side to the first side.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a first bonding pad layer comprising a plurality of first bonding pads on a first side of the base substrate;
a second bonding pad layer comprising a plurality of second bonding pads on a second side of the base substrate, wherein the second side is opposite to the first side; and
a plurality of signal lines on a side of the second bonding pad layer away from the base substrate;
wherein the plurality of signal lines are respectively electrically connected to the plurality of second bonding pads;
a respective one of the plurality of second bonding pads extends through the base substrate to electrically connect to a respective one of the plurality of first bonding pads; and
the respective one of the plurality of first bonding pads comprises a protruding portion protruding away from the first side of the base substrate along a direction from the second side to the first side.

2. The array substrate of claim 1 , wherein an orthographic projection of the respective one of the plurality of second bonding pads on the base substrate at least partially overlaps with an orthographic projection of the respective one of the plurality of first bonding pads on the base substrate.

3. The array substrate of claim 1 , wherein the respective one of the plurality of first bonding pads further comprises a base portion recessing into the first side of the base substrate along a direction from the first side to the second side; and
the respective one of the plurality of second bonding pads is electrically connected to the protruding portion of the respective one of the plurality of first bonding pads through the base portion of the respective one of the plurality of first bonding pads.

4. The array substrate of claim 3 , wherein an orthographic projection of the base portion on the base substrate covers an orthographic projection of the protruding portion on the base substrate.

5. The array substrate of claim 1 , wherein the protruding portion has a thickness relative to the first side of the base substrate along the direction from the second side to the first side greater than 500 nm.

6. The array substrate of claim 1 , wherein the plurality of signal lines comprise a plurality of gate lines and a plurality of data lines;
the plurality of first bonding pads comprise a plurality of first gate line bonding pads and a plurality of first data line bonding pads;
the plurality of second bonding pads comprise a plurality of second gate line bonding pads and a plurality of second data line bonding pads;
the plurality of first gate line bonding pads are respectively electrically connected to the plurality of gate lines respectively through the plurality of second gate line bonding pads; and
the plurality of first data line bonding pads are respectively electrically connected to the plurality of data lines respectively through the plurality of second data line bonding pads.

7. The array substrate of claim 1 , wherein the first bonding pad layer has a multiple sub-layer structure.

8. A display apparatus, comprising the array substrate of claim 1 , and one or more integrated driving circuits connected to the array substrate;
wherein the one or more integrated driving circuits are attached to the first side of the base substrate.

9. A method of fabricating an array substrate, comprising:
forming a first bonding pad layer comprising a plurality of first bonding pads on a first side of a base substrate;
forming a second bonding pad layer comprising a plurality of second bonding pads on a second side of the base substrate, wherein the second side is opposite to the first side; and
forming a plurality of signal lines on a side of the second bonding pad layer away from the base substrate;
wherein the plurality of signal lines are respectively electrically connected to the plurality of second bonding pads;
a respective one of the plurality of second bonding pads extends through the base substrate to electrically connect to a respective one of the plurality of first bonding pads; and
the respective one of the plurality of first bonding pads comprises a protruding portion protruding away from the first side of the base substrate along a direction from the second side to the first side.

10. The method of claim 9 , wherein forming the first bonding pad layer comprises:
providing a support substrate;
forming a plurality of first vias in the support substrate or in a layer on the support substrate;
forming a first conductive material layer at least partially filling in the plurality of first vias; and
patterning the first conductive material layer to obtain the plurality of first bonding pads, thereby forming the first bonding pad layer.

11. The method of claim 10 , wherein forming the plurality of first vias comprises:
forming a first insulating material layer on the support substrate;
wherein the plurality of first vias are formed at least partially extending into the first insulating material layer; and
the first conductive material layer is formed on a side of the first insulating material layer away from the support substrate.

12. The method of claim 10 , wherein forming the plurality of first vias comprises:
patterning the support substrate to form the plurality of first vias;
wherein the plurality of first vias at least partially extend into the support substrate; and
the first conductive material layer is formed on the support substrate.

13. The method of claim 11 , subsequent to forming the first bonding pad layer, further comprising:
forming a second insulating material layer on a side of the first bonding pad layer away from the first insulating material layer;
forming a plurality of second vias extending through the second insulating material layer, thereby forming the base substrate;
forming a second conductive material layer on a side of the base substrate away from the first bonding pad layer, wherein the second conductive material layer at least partially fills in the plurality of second vias; and
patterning the second conductive material layer to obtain the plurality of second bonding pads, thereby forming the second bonding pad layer.

14. The method of claim 13 , subsequent to forming the plurality of first vias and prior to forming the first conductive material layer, further comprising forming a debonding layer on the support substrate;
wherein the first conductive material layer and the base substrate are formed on a side of the debonding layer away from the support substrate.

15. The method of claim 14 , wherein the debonding layer is formed to be in direct contact with the support substrate; and
the debonding layer has a first adhesive strength to the support substrate, a second adhesive strength to the base substrate, and a third adhesive strength to the first bonding pad layer, the first adhesive strength being greater than the second adhesive strength and greater than the third adhesive strength.

16. The method of claim 14 , subsequent to forming the plurality of first vias and prior to forming the first conductive material layer, further comprising:
forming an intermediate layer on a side of the first insulating material layer away from the support substrate;
wherein the debonding layer is formed on a side of the intermediate layer away from the first insulating material layer; and
the debonding layer has a first adhesive strength to the intermediate layer, a second adhesive strength to the base substrate, and a third adhesive strength to the first bonding pad layer, the first adhesive str

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liang Zhiwei
• Di Muxin
• Wang Ke
• Liu Yingwei
• Zhu Xiaoyan
• Cao Zhanfeng
• Yuan Guangcai

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/227

  Multiple bumps having different sizes · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title