Low impedance multi-conductor layered bus structure with shielding

Patent metadata

Field	Value
Publication number	US-11335649-B2
Application number	US-202016879078-A
Country	US
Kind code	B2
Filing date	May 20, 2020
Priority date	May 20, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.

First claim

Therefore, at least the following is claimed:

1. A laminated planar bus structure with stacked layers, comprising:
a plurality of conductive layers arranged in a stack, the plurality of conductive layers comprising:
a plurality of conductive ground layers, the plurality of conductive ground layers comprising an upper ground layer and a lower ground layer;
a positive conductive layer with respect to the plurality of conductive ground layers, the positive conductive layer having a potential greater than the plurality of conductive ground layers;
a negative conductive layer with respect to the plurality of conductive ground layers, the negative conductive layer having a potential less than the plurality of conductive ground layers; and
a fifth conductive layer and a sixth conductive layer, wherein
the upper ground layer and the lower ground layer are arranged as outer layers in the stack with respect to the positive conductive layer and the negative conductive layer, and the fifth and the sixth conductive layers are arranged as outer layers in the stack with respect to the upper ground layer and the lower ground layer;

a plurality of insulation layers separating the plurality of conductive layers, wherein a middle insulation layer separating the positive conductive layer and the negative conductive layer is thicker than an upper insulation layer and a lower insulation layer in the laminated planar bus structure; and
a plurality of apertures through at least one layer of the laminated planar bus structure, an exposed region of at least one of the plurality of conductive layers extending at least in part through at least one of the plurality of apertures.

2. The laminated planar bus structure of claim 1 , wherein the laminated planar bus structure is constructed as a printed circuit board.

3. The laminated planar bus structure of claim 1 , wherein a ratio of an insulation thickness of the middle insulation layer to an insulation thickness of one of the upper insulation layer or the lower insulation layer is about 2:1.

4. The laminated planar bus structure of claim 1 , wherein the upper insulation layer and the lower insulation layer are substantially equal in thickness.

5. The laminated planar bus structure of claim 1 , further comprising:
a top insulation layer over the upper ground layer and the upper insulation layer in the stack; and
a bottom insulation layer stacked under the lower ground layer and the lower insulation layer in the stack.

6. The laminated planar bus structure of claim 1 , wherein the plurality of apertures comprise:
a positive aperture with an exposed region of the positive conductive layer; and
a negative aperture with an exposed region of the negative conductive layer.

7. The laminated planar bus structure of claim 1 , wherein each of the plurality of conductive layers is formed of substantially equal thicknesses.

8. A planar bus structure with stacked layers, comprising:
a plurality of conductive layers arranged in a stack, the plurality of conductive layers comprising:
a plurality of conductive ground layers, the plurality of conductive ground layers comprising an upper ground layer, a middle ground layer, and a lower ground layer;
a positive conductive layer with respect to the plurality of conductive ground layers, the positive conductive layer having a potential greater than the plurality of conductive ground layers; and
a negative conductive layer with respect to the plurality of conductive ground layers, the negative conductive layer having a potential less than the plurality of conductive ground layers,
wherein the upper ground layer and the lower ground layer are arranged as outer layers in the stack with respect to the positive conductive layer and the negative conductive layer,
wherein the middle ground layer is arranged in the stack between the positive conductive layer and the negative conductive layer; and

a plurality of insulation layers separating the plurality of conductive layers.

9. The planar bus structure of claim 8 , further comprising a plurality of apertures through at least one layer of the planar bus structure, at least one of the plurality of apertures comprising an exposed region of at least one of the plurality of conductive layers.

10. The planar bus structure of claim 8 , wherein the plurality of conductive layers arranged in the stack further comprise a sixth conductive layer and a seventh conductive layer, the sixth and the seventh conductive layers arranged as outer layers in the stack with respect to the upper ground layer and the lower ground layer.

11. The planar bus structure of claim 8 , further comprising a plurality of passthrough holes extending from one surface of the planar bus structure to an opposite surface of the planar bus structure.

12. The planar bus structure of claim 8 , further comprising an offset between one distal edge of the middle ground layer to a distal edge of the positive conductive layer.

13. The planar bus structure of claim 12 , wherein the offset is at least about 1 millimeter.

14. The planar bus structure of claim 8 , wherein a clearance between an edge of the planar bus structure to an edge of the middle ground layer is at least about 6 mm.

15. The planar bus structure of claim 8 , wherein the plurality of insulation layers comprise a top insulation layer over the upper ground layer in the stack and a bottom insulation layer under the lower ground layer in the stack.

16. The planar bus structure of claim 8 , further comprising straight bus terminals, bent bus terminals, or no bus terminals.

17. A power converter, comprising:
a planar bus structure comprising a plurality of conductive layers arranged in a stack, the plurality of conductive layers comprising:
a plurality of conductive ground layers, the plurality of conductive ground layers comprising an upper ground layer, a middle ground layer, and a lower ground layer;
a positive conductive layer with respect to the plurality of conductive ground layers, the positive conductive layer having a potential greater than the plurality of conductive ground layers; and
a negative conductive layer with respect to the plurality of conductive ground layers, the negative conductive layer having a potential less than the plurality of conductive ground layers,
wherein the middle ground layer is arranged in the stack between the positive conductive layer and the negative conductive layer;

a set of power modules connected to the positive conductive layer and the negative conductive layer; and
a set of gate drivers connected to the set of power modules through passthrough holes in the planar bus structure.

18. The power converter of claim 17 , wherein the upper ground layer and the lower ground layer are arranged as outer layers in the stack with respect to the positive conductive layer and the negative conductive layer.

19. The power converter of claim 17 , wherein the set of power modules is arranged under the planar bus structure and the set of gate drivers is arranged over the planar bus structure.

Assignees

• Virginia Tech Intellectual Properties Inc

Inventors

• Wang Jun
• Burgos Rolando
• Boroyevich Dushan
• Stewart Joshua
• Xu Yue

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H05K7/14329

  specially adapted for the configuration of power bus bars · CPC title

• H02M1/44 Primary

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title