Multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-11335509-B2
Application number	US-202016788345-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	Feb 22, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A multilayer ceramic capacitor includes a ceramic body including a stack of dielectric layers and internal electrodes, and an external electrode electrically connected to each of the internal electrodes and provided at each of both end surfaces of the ceramic body. The external electrode includes a metal layer and a plating layer on the metal layer. In a cross section of the metal layer that is obtained by cutting the external electrode along a plane parallel to a side surface at a central position in a width direction, the metal layer includes a dielectric material at an area ratio of about 20% or more, and includes cavities at an area ratio of about 5% or more and about 20% or less, the cavities having an average diameter of about 0.5 μm or more and about 1.5 μm or less, and having a maximum diameter of about 5.0 μm or less.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a ceramic body including a stack of a plurality of dielectric layers and a plurality of internal electrodes, the ceramic body including:
a first main surface and a second main surface that face each other in a stacking direction;
a first side surface and a second side surface that face each other in a width direction orthogonal or substantially orthogonal to the stacking direction; and
a first end surface and a second end surface that face each other in a length direction orthogonal or substantially orthogonal to the stacking direction and the width direction; and

an external electrode electrically connected to each of the plurality of internal electrodes and provided at each of the first end surface and the second end surface of the ceramic body; wherein
the external electrode includes a metal layer and a plating layer on the metal layer;
in a cross section of the metal layer that is obtained by cutting the external electrode along a plane parallel or substantially parallel to the first side surface and the second side surface at a central position in the width direction, the metal layer includes a dielectric material at an area ratio of about 20% or more, and includes a plurality of cavities at an area ratio of about 5% or more and about 20% or less, the cavities having an average diameter of about 0.5 μm or more and about 1.5 μm or less, and having a maximum diameter of about 5.0 μm or less.

2. The multilayer ceramic capacitor according to claim 1 , wherein the metal layer includes Ni.

3. The multilayer ceramic capacitor according to claim 1 , wherein the plating layer includes Cu.

4. The multilayer ceramic capacitor according to claim 1 , wherein a relationship of DT<DW<DL is established, where DT denotes a dimension of the ceramic body in the stacking direction, DW denotes a dimension of the ceramic body in the width direction, and DL denotes a dimension of the ceramic body in the length direction.

5. The multilayer ceramic capacitor according to claim 4 , wherein the dimension DT of the ceramic body in the stacking direction is about 0.05 mm or more and about 0.25 mm or less.

6. The multilayer ceramic capacitor according to claim 1 , wherein the ceramic body includes corner portions and ridgeline portions that are rounded.

7. The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of dielectric layers is made of at least one of BaTiO 3 , CaTiO 3 , SrTiO 3 , or CaZrO 3 as a main component.

8. The multilayer ceramic capacitor according to claim 7 , wherein each of the plurality of dielectric layers includes at least one of a Cr compound, a Co compound, or an Ni compound as a sub-component.

9. The multilayer ceramic capacitor according to claim 1 , wherein the plurality of dielectric layers include inner dielectric layers and outer dielectric layers sandwiching the inner dielectric layer in the stacking direction.

10. The multilayer ceramic capacitor according to claim 9 , wherein each of the outer dielectric layers has a thickness of about 10 μm or more and about 30 μm or less.

11. The multilayer ceramic capacitor according to claim 9 , wherein each of the inner dielectric layers has a thickness of about 0.4 μm or more and about 0.8 μm or less.

12. The multilayer ceramic capacitor according to claim 9 , wherein a number of dielectric layers included in the inner and outer dielectric layers is 10 or more and 200 or less.

13. The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrodes includes at least one of Cu, Ni, Ag, Pd, Ti, Cr, or Au, or an alloy including at least one of Cu, Ni, Ag, Pd, Ti, Cr, or Au as main components.

14. The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrodes has a thickness of about 0.3 μm μm or more and about 0.8 μm or less.

15. The multilayer ceramic capacitor according to claim 1 , wherein a number of the plurality of internal electrodes is 10 or more and 30 or less.

16. The multilayer ceramic capacitor according to claim 1 , wherein
the metal layer does not include glass; and
the external electrode is partially embedded into the ceramic body.

Assignees

• Murata Manufacturing Co

Inventors

• Sasabayashi Takehisa
• Doi Akitaka
• Shimizu Kotaro
• Okabe Yoko

Classifications

• H01G4/1209

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title

• H01G4/012 Primary

  Form of non-self-supporting electrodes · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/02

  Gas or vapour dielectrics · CPC title