Display panel with different pixel density and display device

US11335246B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11335246-B2
Application numberUS-202017020127-A
CountryUS
Kind codeB2
Filing dateSep 14, 2020
Priority dateJul 28, 2020
Publication dateMay 17, 2022
Grant dateMay 17, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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A display panel and a display device are provided in the present disclosure. The display panel includes first pixels and second pixels, and further includes a display region including an optical component region and a regular display region. First light-emitting elements are in the optical component region; second light-emitting elements are in the regular display region; and a density of the light-emitting elements in the optical component region is less than a density of the light-emitting elements in the regular display region. The first pixels include first blue pixels, first red pixels, and first green pixels; a width-to-length ratio of a first drive transistor corresponding to a first blue pixel is R1, a width-to-length ratio of a first drive transistor corresponding to a first red pixel is R2, and a width-to-length ratio of a first drive transistor corresponding to a first green pixel is R3, where R1>R2>0 and/or R1>R3>0.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a plurality of pixels, including first pixels and second pixels, wherein a first pixel includes a first light-emitting element and a first pixel circuit, connected to each other; the first pixel circuit includes a first drive transistor; a second pixel includes a second light-emitting element and a second pixel circuit, connected to each other; and the second pixel circuit includes a second drive transistor; and a display region, including an optical component region and a regular display region, wherein the first light-emitting element is in the optical component region; the second light-emitting element is in the regular display region; a density of the light-emitting element in the optical component region is less than a density of the light-emitting element in the regular display region, wherein: the first pixels include first blue pixels, first red pixels, and first green pixels; a channel width-to-length ratio of a first drive transistor corresponding to a first blue pixel is R1, a channel width-to-length ratio of a first drive transistor corresponding to a first red pixel is R2, and a channel width-to-length ratio of a first drive transistor corresponding to a first green pixel is R3, wherein R1>R2>0 and/or R1>R3>0, the second pixels include second blue pixels, second red pixels, and second green pixels; a channel width-to-length ratio of a second drive transistor corresponding to a second blue pixel is R1′, a channel width-to-length ratio of a second drive transistor corresponding to a second red pixel is R2′, and a channel width-to-length ratio of a second drive transistor corresponding to a second green pixel is R3′, and R1>R1′, R2>R2′, and R3>R3′. 2. The display panel according to claim 1 , wherein: 2≤R1/R2≤4, and/or 2≤R1/R3≤4. 3. The display panel according to claim 1 , wherein: the first pixel circuit includes a reset module, a data write module, and a light-emitting control module which are electrically connected to the first drive transistor; the reset module includes at least one reset transistor electrically connected to the first drive transistor; the data write module includes at least one data write transistor electrically connected to the first drive transistor; and the light-emitting control module includes at least one light-emitting control transistor electrically connected to the first drive transistor; and a channel width-to-length ratio of a light-emitting control transistor corresponding to the first pixel circuit is greater than each of channel width-to-length ratios of the reset transistor and the data write transistor in a same first pixel circuit. 4. The display panel according to claim 3 , wherein: the first pixel circuit further includes a black state maintaining module electrically connected to the first light-emitting element, and the black state maintaining module includes at least one black state maintaining transistor electrically connected to the first light-emitting element; and the channel width-to-length ratio of the light-emitting control transistor corresponding to the first pixel circuit is greater than a channel width-to-length ratio of the black state maintaining transistor in a same first pixel circuit. 5. The display panel according to claim 3 , wherein: a channel width-to-length ratio of a light-emitting control transistor corresponding to the first blue pixel is R k 1; a channel width-to-length ratio of a light-emitting control transistor corresponding to the first red pixel is R k 2; and a channel width-to-length ratio of a light-emitting control transistor corresponding to the first green pixel is R k 3, wherein when R1>R2>0, R k 1>R k 2>0; and when R1>R3>0, R k 1>R k 3>0. 6. The display panel according to claim 3 , wherein: the channel width-to-length ratio of the light-emitting control transistor corresponding to the first pixel circuit is R k , wherein 4≤R k ≤6. 7. The display panel according to claim 1 , wherein: the first pixel circuit includes a first storage capacitor electrically connected to a gate electrode of the first drive transistor; the second pixel circuit includes a second storage capacitor electrically connected to a gate electrode of the second drive transistor; and a capacitance of the first storage capacitor is greater than a capacitance of the second storage capacitor. 8. The display panel according to claim 7 , wherein: the capacitance of the first storage capacitor is C1, and the capacitance of the second storage capacitor is C2, wherein 2≤C1/C2≤4. 9. The display panel according to claim 1 , wherein: R1′>R2′>0 and/or R1′>R3′>0. 10. The display panel according to claim 9 , wherein: a channel width of the second drive transistor corresponding to the second red pixel is W2′, a channel width of the second drive transistor corresponding to the second green pixel is W3′, a channel length of the second drive transistor corresponding to the second red pixel is L2′, and a channel length of the second drive transistor corresponding to the second green pixel is L3′, wherein |W2′-W3′|≤0.5 μm, and |L2′-L3′|≤0.5 μm. 11. The display panel according to claim 9 , wherein: any one of the first pixel circuit and the second pixel circuit includes an anode voltage terminal and a cathode voltage terminal, wherein: the anode voltage terminal of the first pixel circuit and the anode voltage terminal of the second pixel circuit are both electrically connected to a same voltage terminal; and the cathode voltage terminal of the first pixel circuit and the cathode voltage terminal of the second pixel circuit are both electrically connected to a same voltage terminal. 12. The display panel according to claim 1 , wherein: a ratio of a channel width-to-length ratio of the first drive transistor corresponding to any color pixel to a channel width-to-length ratio of the second drive transistor corresponding to a same color pixel is S, wherein 3.5≤S≤5. 13. The display panel according to claim 1 , wherein: in the first drive transistor corresponding to the first blue pixel, the first drive transistor corresponding to the first red pixel, the first drive transistor corresponding to the first green pixel, at least the first drive transistor corresponding to the first blue pixel has a channel in a rectangular shape. 14. A display panel, comprising: a plurality of pixels, including first pixels and second pixels, wherein a first pixel includes a first light-emitting element and a first pixel circuit, connected to each other; the first pixel circuit includes a first drive transistor; a second pixel includes a second light-emitting element and a second pixel circuit, connected to each other; and the second pixel circuit includes a second drive transistor; and a display region, including an optical component region and a regular display region, wherein the first light-emitting element is in the optical component region; the second light-emitting element is in the regular display region; a density of the light-emitting element in the optical component region is less than a density of the light-emitting element in the regular display region, wherein: the first pixels include first blue pixels, first red pixels, and first green pixels; a width-to-length ratio of a first drive transistor corresponding to a first blue pixel is R1, a width-to-length ratio of a first drive transistor corresponding to a first red pixel is R2, and a width-to-length ratio of a first drive transistor corresponding to a first green pixel is R3, wherein R1>R2>0 and/or R1>R3>0, and a channel width of the first drive transistor corresponding to th

Assignees

Inventors

Classifications

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

  • Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

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What does patent US11335246B2 cover?
A display panel and a display device are provided in the present disclosure. The display panel includes first pixels and second pixels, and further includes a display region including an optical component region and a regular display region. First light-emitting elements are in the optical component region; second light-emitting elements are in the regular display region; and a density of the l…
Who is the assignee on this patent?
Wuhan Tianma Micro Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 17 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).