Method and system for fault collection and reaction in system-on-chip

Patent metadata

Field	Value
Publication number	US-11334409-B2
Application number	US-202017003457-A
Country	US
Kind code	B2
Filing date	Aug 26, 2020
Priority date	Jun 18, 2020
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A fault collection and reaction system on a system-on-chip (SoC) includes a plurality of reaction cores assigned to a plurality of applications being executed by a plurality of processor cores on the SoC, at least one look-up table (LUT), and a controller. The at least one LUT stores therein a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations. The controller receives a fault indication and a first domain identifier in response to occurrence of a first fault and selects from the plurality of reaction cores, a first reaction core mapped to the first domain identifier, and from the set of reaction combinations, a first reaction combination mapped to the first fault. The first reaction core responds to the fault indication with a reaction based on the selected reaction combination.

First claim

The invention claimed is:

1. A system-on-chip (SoC), comprising:
a plurality of processor cores configured to execute a plurality of applications;
a fault collection and reaction system coupled to the plurality of processor cores, the fault collection and reaction system comprising:
a plurality of reaction cores each assigned to at least one of the plurality of applications;
at least one look-up-table (LUT) configured to store a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults associated with the plurality of applications and a set of reaction combinations; and
a controller coupled to the plurality of reaction cores and the at least one LUT, and configured to:
receive a fault indication and a first domain identifier of the plurality of domain identifiers in response to occurrence of a first fault associated with a first application of the plurality of applications; and
select from the plurality of reaction cores, a first reaction core mapped to the first domain identifier in the at least one LUT, and from the set of reaction combinations, a first reaction combination mapped to the first fault in the at least one LUT, wherein the selected first reaction core is configured to:
respond to the fault indication with a reaction based on the selected reaction combination.

2. The SoC of claim 1 , further comprising:
at least one resource coupled to the fault collection and reaction system and the plurality of processor cores, wherein the execution of the plurality of applications comprises a plurality of transactions between the at least one resource and the plurality of processor cores, and wherein the first fault occurs based on at least one of a failure of a first transaction associated with the first application and a failure of an operation of the at least one resource subsequent to the first transaction.

3. The SoC of claim 1 , wherein the first reaction core comprises:
a set of immediate reaction LUTs, wherein each of the set of immediate reaction LUTs is configured to store therein an immediate reaction configuration corresponding to at least one of the plurality of faults; and
a set of delayed reaction LUTs, wherein each of the set of delayed reaction LUTs is configured to store therein a delayed reaction configuration corresponding to at least one of the plurality of faults.

4. The SoC of claim 3 , wherein the controller is further configured to:
generate a first selection signal to indicate the selection of the first reaction core;
provide the first selection signal to the plurality of reaction cores, wherein based on the first selection signal, the first reaction core assigned to the first application and mapped to the first domain identifier is selected from the plurality of reaction cores to respond to the fault indication;
generate a second selection signal to indicate the selection of the first reaction combination; and
provide the second selection signal to the selected first reaction core.

5. The SoC of claim 4 , wherein the set of immediate reaction LUTs and the set of delayed reaction LUTs are further configured to receive the second selection signal, and wherein based on the second selection signal, a first immediate reaction LUT and a first delayed reaction LUT corresponding to the first reaction combination are selected from the set of immediate reaction LUTs and the set of delayed reaction LUTs, respectively, to respond to the fault indication.

6. The SoC of claim 5 , wherein the controller is further configured to generate a start signal based on the received fault indication, and a reset signal when the first fault is handled.

7. The SoC of claim 6 , wherein the fault collection and reaction system further comprises:
a timer coupled to the controller and the plurality of reaction cores, and configured to:
receive the start signal from the controller;
run based on a timer value indicated by the start signal;
generate a time-out signal, wherein the time-out signal transitions from a first logic state to a second logic state when the timer times out;
receive the reset signal from the controller when the first fault is handled; and
reset to a default state based on the reset signal.

8. The SoC of claim 7 , wherein the set of delayed reaction LUTs is further configured to receive the time-out signal, and wherein the first delayed reaction LUT selected based on the second selection signal is disabled when the time-out signal is at the first logic state and enabled when the time-out signal is at the second logic state.

9. The SoC of claim 7 , wherein when the time-out signal is at the first logic state, the first immediate reaction LUT is configured to output the reaction based on a first immediate reaction configuration stored therein, and wherein when the time-out signal is at the second logic state, the first delayed reaction LUT is configured to output the reaction based on a first delayed reaction configuration stored therein.

10. A fault collection and reaction method for a system-on-chip (SoC), the fault collection and reaction method comprising:
storing, by at least one look-up table (LUT) of a fault collection and reaction system on the SoC, a first mapping between a plurality of reaction cores of the fault collection and reaction system and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations, wherein the plurality of faults are associated with a plurality of applications executed by a plurality of processor cores on the SoC and each of the plurality of reaction cores is assigned to at least one of the plurality of applications;
receiving, by a controller of the fault collection and reaction system, a fault indication and a first domain identifier of the plurality of domain identifiers in response to occurrence of a first fault associated with a first application of the plurality of applications;
selecting, by the controller, from the plurality of reaction cores, a first reaction core mapped to the first domain identifier in the at least one LUT, and from the set of reaction combinations, a first reaction combination mapped to the first fault in the at least one LUT; and
responding, by the selected first reaction core, to the fault indication with a reaction based on the selected first reaction combination.

11. The fault collection and reaction method of claim 10 , wherein the first fault occurs based on at least one of a failure in the execution of the first application and a failure of an operation performed by a resource on the SoC in response to the execution of the first application.

12. The fault collection and reaction method of claim 10 , further comprising:
generating, by the controller, a first selection signal to indicate the selection of the first reaction core;
providing, by the controller to the plurality of reaction cores, the first selection signal, wherein based on the first selection signal, the first reaction core assigned to the first application and mapped to the first domain identifier is selected from the plurality of reaction cores for responding to the fault indication;
generating, by the controller, a second selection signal to indicate the selection of the first reaction combination; and
providing, by the controller, the second selection signal to the selected first reaction core.

13. The fault collection and reaction method of claim 12 , further comprising:
storing, by each of a set of immediate reaction LUTs of the first reaction core, an immediate reaction configuration corresponding to

Assignees

• Nxp Usa Inc

Inventors

• Nautiyal Hemant
• Refaeli Jehoda
• Sethi Ankush
• Singh Shreya

Classifications

• G06F11/0709

  in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems · CPC title

• G06F11/0775

  Content or structure details of the error report, e.g. specific table structure, specific error fields · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0724 Primary

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title