Non-overlapping power/ground planes for localized power distribution network design

Patent metadata

Field	Value
Publication number	US-11330699-B2
Application number	US-201716467895-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Dec 15, 2016
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Embodiments described herein are directed to methods and apparatus for power distribution. The apparatus can include a power distribution network for a plurality of integrated circuits (IC). According to embodiments, the power distribution network includes a plurality of overlapping power/ground (PG) plane segments and one or more non-overlapping PG (no-PG) plane segments. Each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment. The no-PG plane segments can include at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.

First claim

What is claimed is:

1. An apparatus for power distribution, comprising:
a power distribution network for a plurality of integrated circuits (IC), wherein
the power distribution network includes a plurality of overlapping power/ground (PG) plane segments and one or more non-overlapping PG (no-PG) plane segments, and
each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment,
where the one or more no-PG plane segments comprise at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.

2. The apparatus of claim 1 , wherein each of the at least one no-PG plane segment comprises a power (P) plane segment or a ground (G) plane segment.

3. The apparatus of claim 2 , wherein each P plane segment is separated from each G plane segment by a predetermined gap to reduce parasitic gap capacitance.

4. The apparatus of claim 1 , wherein power planes in the at least one multilayer P plane segment are shorted with each other using a plurality of vias to provide a parallel current path for direct current.

5. The apparatus of claim 1 , wherein ground planes in the at least one multilayer G plane segment are shorted with each other using a plurality of vias to provide a parallel current path for direct current.

6. The apparatus of claim 1 , wherein each multilayer P plane segment is separated from each multilayer G plane segment by a predetermined gap to reduce parasitic gap capacitance.

7. The apparatus of claim 1 , wherein each IC is assembled on an overlapping PG plane segment.

8. The apparatus of claim 1 , wherein the apparatus is a printed circuit board.

9. The apparatus of claim 1 , wherein the apparatus is a chip package.

10. A method of assembling a power distribution network for a plurality of integrated circuits (IC), comprising:
overlapping a plurality of power/ground (PG) plane segments of power and ground planes; and
forming at least one portion of at least one of the power and ground planes to form one or more non-overlapping PG (no-PG) plane segments, such that each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment,
where the one or more no-PG plane segments comprise at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.

11. The method of claim 10 , wherein each of the at least one no-PG plane segment comprises a power (P) plane segment or a ground (G) plane segment.

12. The method of claim 11 , wherein each P plane segment is separated from each G plane segment by a predetermined gap to reduce parasitic gap capacitance.

13. The method of claim 10 , further comprising:
shorting power planes in the at least one multilayer P plane segment with each other using a plurality of vias to provide a parallel current path for direct current.

14. The method of claim 10 , further comprising:
shorting ground planes in the at least one multilayer G plane segment with each other using a plurality of vias to provide a parallel current path for direct current.

15. The method of claim 10 , further comprising:
separating each multilayer P plane segment from each multilayer G plane segment by a predetermined gap to reduce parasitic gap capacitance.

16. The method of claim 10 , wherein each IC is assembled on an overlapping PG plane segment.

17. The method of claim 10 , wherein the forming of the one or more no-PG plane segments comprises determining which portion of power and/or ground planes is a location for a no-PG plane segment, based on one or more of a board size, one or more port locations, plane and ground segment separation distance, a desired length of the no-PG plane segments, and IR-drop.

18. The method of claim 10 , wherein the power distribution network is assembled on a printed circuit board.

19. The method of claim 10 , wherein the power distribution network is assembled on a chip package.

20. A non-transitory computer-readable medium, storing instructions thereon which, when executed by one or more processors, perform the method of claim 10 .

Assignees

• San Diego State Univ Research Foundation
• Kyocera Int Inc
• Fraunhofer Ges Forschung

Inventors

• Engin Arif Ege
• Aguirre Gerardo
• Lang Klaus-Dieter
• Ndip Ivan

Classifications

• H05K1/0236

  Electromagnetic band-gap structures · CPC title

• H05K2201/0792

  Means against parasitic impedance; Means against eddy currents · CPC title

• H05K2201/09309

  Core having two or more power planes; Capacitive laminate of two power planes · CPC title

• H05K1/0227 Primary

  Split or nearly split shielding or ground planes · CPC title

• H05K2201/09345

  Power and ground in the same plane; Power planes for two voltages in one plane · CPC title