Sensor arrangement and method for dark count cancellation

Patent metadata

Field	Value
Publication number	US-11330216-B2
Application number	US-201917415324-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Dec 21, 2018
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A sensor arrangement for light sensing for light-to-frequency conversion. The sensor arrangement includes a photodiode, an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK1), and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing the digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of chopping switches coupled to a first amplifier, a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

First claim

What is claimed is:

1. A sensor arrangement for light-to-frequency conversion, comprising:
a photodiode;
an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK 1 ), and operable to convert a photocurrent (IPD) generated by the photodiode into a digital comparator output signal (LOUT), the ADC comprising:
a sensor input coupled to the photodiode;
a result output for providing the digital comparator output signal (LOUT);
an integrator comprising:
an integrator input coupled to the sensor input and operable to receive an integrator input signal;
a first and a second amplifier;
a first set of chopping switches electrically coupled to input terminals of the first amplifier;
a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of the second amplifier; and
an integrator output providing an integrator output signal (OPOUT); and

a signal processing unit coupled to the result output of the ADC and configured to determine, from the digital comparator output signal (LOUT), a digital output signal (ADC-COUNT).

2. The sensor arrangement of claim 1 , wherein the ADC is operable to perform, prior to performing the chopping the technique, an initial phase comprising:
applying a coarse auto zero operation before a start of an integration time (T_INT) for an integration cycle; and
applying a first reset/initialization phase that resets the ADC and signal acquisition is initialized at the start of the integration time (T_INT) for the integration cycle.

3. The sensor arrangement of claim 2 , wherein the ADC is operable to perform, subsequent to performing the initial phase, a first chopping technique comprising:
applying a first phase of chopping at the first set of chopping switches and the second set of chopping switches, wherein the first phase of chopping is applied at a first polarity; and
applying, at a halfway timestamp and without stopping the integration cycle, a second phase of chopping at the first set of chopping switches and the second set of chopping switches, the halfway timestamp indicating a halfway point of the integration time (T_INT), wherein the second phase of chopping is applied at a second polarity, wherein the second polarity is opposite of the first polarity.

4. The sensor arrangement of claim 2 , wherein the ADC is operable to perform, subsequent to performing the initial phase, a second chopping technique comprising:
applying, at a halfway timestamp, a first phase of chopping at the first set of chopping switches and the second set of chopping switches, the halfway timestamp indicating a halfway point of an integration time (T_INT) for the integration cycle, wherein the first phase of chopping is applied at a first polarity;
applying a second reset/initialization phase that resets the ADC and signal acquisition is re-initialized at the halfway point of the integration time (T_INT) for the integration cycle, wherein the second reset/initialization phase stops the integration cycle and changes a polarity of the integrator output; and
applying, after the second reset/initialization phase, a second phase of chopping at the first set of chopping switches and the second set of chopping switches, wherein the second phase of chopping is applied at the first polarity.

5. The sensor arrangement of claim 4 , wherein changing the polarity of the integrator output comprises:
switching the output of the first set of chopping switches for the input terminals of the first amplifier; and
switching the output of the second set of chopping switches for the input terminals of the second amplifier.

6. The sensor arrangement of claim 1 , wherein the signal processing unit comprises:
a first counter having a first clock input coupled to the result output and comprising a first reset input;
a second counter comprising a second clock input and a second reset input; and
a logic/calculation engine comprising a calculation input coupled to a first counter output of the first counter and a second counter output of the second counter;
wherein:
the first counter is operable to receive the first clock signal (CLK 1 ) at the first clock input and to generate the asynchronous count (C 1 ) depending on the first clock signal (CLK 1 );
the second counter is operable to receive the second clock signal (CLK 2 ) at the second clock input and to generate the time count (C 2 ) depending on the second clock signal (CLK 2 ); and
the logic/calculation engine is operable to receive the asynchronous count (C 1 ) and the time count (C 2 ) and to calculate the digital output signal (ADC-COUNT) from the asynchronous count (C 1 ) and the time count (C 2 ).

7. The sensor arrangement of claim 1 , further comprising a latched comparator operable receive the integrator output signal (OPOUT) and to provide the digital comparator output signal (LOUT).

8. The sensor arrangement of claim 1 , further comprising a digital control circuit operable to control each switch to switch between an open state and a closed state depending on a clock cycle.

9. The sensor arrangement of claim 1 , wherein the digital output signal (ADC-COUNT) comprises an asynchronous count (C 1 ) comprising an integer number of counts depending on the first clock signal (CLK 1 ) and a fractional time count (C 2 ) depending on a second clock signal (CLK 2 ).

10. The sensor arrangement of claim 1 , wherein the digital output signal (ADC-COUNT) is indicative of the photocurrent generated by the photodiode.

11. The sensor arrangement of claim 1 , the signal processing unit is configured to determine, based on the time count, an average integration period indicative of a modulation in the digital comparator output signal (LOUT).

12. A method for light-to-frequency conversion comprising:
generating, by an offset voltage across a photodiode, a photocurrent (IPD);
converting, by an analog-to-digital converter (ADC), and based on a chopping technique performed during an integration cycle, the photocurrent (IPD) into a digital comparator output signal (LOUT) depending on a first clock signal (CLK 1 ), wherein the ADC comprises an integrator that includes:
a first set of chopping switches electrically coupled to input terminals of a first amplifier;
a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier; and
an integrator output providing an integrator output signal (OPOUT);

determining, based on the digital comparator output signal (LOUT), an asynchronous count (C 1 ) comprising an integer number of counts depending on the first clock signal (CLK 1 );
determining, based on the digital comparator output signal (LOUT), a fractional time count (C 2 ) depending on a second clock signal (CLK 2 ); and
calculating, based on the asynchronous count (C 1 ) and the fractional time count (C 2 ), a digital output signal (ADC-COUNT) which is indicative of the photocurrent generated by the photodiode.

13. The method of claim 12 , wherein converting the photocurrent based on the chopping technique cancels the offset voltage across the photodiode.

14. The method of claim 12 , further comprising, prior to performing the chopping technique, performing an initial phase comprising:
applying a coarse auto zero operation before a start of an integration time (T_INT) for the integration cycle; and
applying a first reset/initialization phase that resets the ADC and signal acquisition is initialized at the start of the integration time (T_INT) for the integr

Assignees

• Ams Ag

Inventors

• Adusumalli Ravi Kumar
• Singamala Sudhakar

Classifications

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H04N25/633

  by using optical black pixels · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H03F3/38

  DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers {(switched capacitor amplifiers H03F3/005)} · CPC title

• H03M1/52

  Input signal integrated with linear return to datum · CPC title