Current source circuit

Patent metadata

Field	Value
Publication number	US-11329648-B2
Application number	US-202117180300-A
Country	US
Kind code	B2
Filing date	Feb 19, 2021
Priority date	Mar 24, 2020
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A discharge control circuit includes discharge elements, logic circuits, and at least one delay circuit. Each of the logic circuits controls turning-on and turning-off the discharge elements based on a control signal inputted externally. The delay circuit delays an output signal of a first logic circuit among the logic circuits. The discharge control circuit pulls out charges from a corresponding terminal in response to turning-on of the discharge elements. A signal delayed by the delay circuit is inputted to a second logic circuit among the logic circuits so that the discharge elements are controlled in a predetermined order by one control signal.

First claim

What is claimed is:

1. A current source circuit that provides a constant current used by a delay circuit, the current source circuit comprising:
a first depletion type MOS transistor that includes a source terminal and a gate terminal; and
a resistance element which has positive temperature characteristics and which is connected between the source terminal of the first depletion type MOS transistor and a power voltage terminal or a ground terminal,
wherein the gate terminal of the first depletion type MOS transistor is connected to the power voltage terminal or the ground terminal, and
wherein a second depletion type MOS transistor and an adjuster circuit including a fuse element or a switch element are connected in parallel or in series with the first depletion type MOS transistor.

2. The current source circuit according to claim 1 , wherein:
the first depletion type MOS transistor is an element formed on a semiconductor chip, and
the resistance element is constituted by a well region formed simultaneously with a well region constituting a substrate of the first depletion type MOS transistor.

3. The current source circuit according to claim 1 , wherein:
the first depletion type MOS transistor is an element formed on a semiconductor chip, and
the resistance element is constituted by an active region formed simultaneously with active regions constituting a source region and a drain region of the first depletion type MOS transistor.

4. The current source circuit according to claim 1 , wherein:
the resistance element is constituted by an enhancement type MOS transistor including a gate terminal to which a predetermined voltage is applied.

5. The current source circuit according to claim 1 , wherein:
the first depletion type MOS transistor is of a N-channel type,
the gate terminal of the first depletion type MOS transistor is connected to the ground terminal, and
the resistance element is connected between the source terminal of the first depletion type MOS transistor and the ground terminal.

6. The current source circuit according to claim 1 , wherein:
the first depletion type MOS transistor is of a P-channel type,
the gate terminal of the first depletion type MOS transistor is connected to the power voltage terminal, and
the resistance element is connected between the source terminal of the first depletion type MOS transistor and the power voltage terminal.

7. The current source circuit according to claim 1 , wherein the delay circuit comprises:
a capacitor that is charged or discharged by a current provided by the current source circuit; and
a voltage comparator circuit that detects a charged voltage of the capacitor.

8. The current source circuit according to claim 1 , wherein
the delay circuit comprises:
an oscillator circuit; and
a counter circuit that counts signals of a predetermined frequency which is generated by the oscillator circuit,
wherein the oscillator circuit comprises:
a capacitor that is charged or discharged by a current provided by the current source circuit; and
a voltage comparator circuit that detects a charged voltage of the capacitor, or an inverter.

9. A delay system comprising a delay circuit and a current source circuit that provides a constant current to the delay circuit, the current source circuit comprising:
a first depletion type MOS transistor that includes a source terminal and a gate terminal; and
a resistance element which has positive temperature characteristics and which is connected between the source terminal of the first depletion type MOS transistor and a power voltage terminal or a ground terminal,
wherein the gate terminal of the first depletion type MOS transistor is connected to the power voltage terminal or the ground terminal, and
wherein the delay circuit comprises:
an oscillator circuit; and
a counter circuit that counts signals of a predetermined frequency which is generated by the oscillator circuit,
wherein the oscillator circuit comprises:
a capacitor that is charged or discharged by the current provided by the current source circuit; and
a voltage comparator circuit that detects a charged voltage of the capacitor, or an inverter, and

wherein an output signal of the counter circuit controls a sequence of power-on and power-off of an external power supply.

10. The delay system according to claim 9 , wherein:
the first depletion type MOS transistor is an element formed on a semiconductor chip, and
the resistance element is constituted by a well region formed simultaneously with a well region constituting a substrate of the first depletion type MOS transistor.

11. The delay system according to claim 9 , wherein:
the first depletion type MOS transistor is an element formed on a semiconductor chip, and
the resistance element is constituted by an active region formed simultaneously with active regions constituting a source region and a drain region of the first depletion type MOS transistor.

12. The delay system according to claim 9 , wherein:
the resistance element is constituted by an enhancement type MOS transistor including a gate terminal to which a predetermined voltage is applied.

13. The delay system according to claim 9 , wherein:
the first depletion type MOS transistor is of an N-channel type,
the gate terminal of the first depletion type MOS transistor is connected to the ground terminal, and
the resistance element is connected between the source terminal of the first depletion type MOS transistor and the ground terminal.

14. The delay system according to claim 9 , wherein:
the first depletion type MOS transistor is of a P-channel type,
the gate terminal of the first depletion type MOS transistor is connected to the power voltage terminal, and
the resistance element is connected between the source terminal of the first depletion type MOS transistor and the power voltage terminal.

15. A delay system comprising a delay circuit and a current source circuit that provides a constant current to the delay circuit, the current source circuit comprising:
a first depletion type MOS transistor that includes a source terminal and a gate terminal; and
a resistance element which has positive temperature characteristics and which is connected between the source terminal of the first depletion type MOS transistor and a power voltage terminal or a ground terminal,
wherein the gate terminal of the first depletion type MOS transistor is connected to the power voltage terminal or the ground terminal, and
wherein the delay circuit comprises:
a capacitor that is charged or discharged by the current provided by the current source circuit;
a voltage comparator circuit that detects a charged voltage of the capacitor; and
a switch that switches, according to an output signal of the voltage comparator circuit, an input to the voltage comparator circuit between a first reference voltage and a second reference voltage which is lower than the first reference voltage.

16. The delay system according to claim 15 , wherein:
the first depletion type MOS transistor is an element formed on a semiconductor chip, and
the resistance element is constituted by a well region formed simultaneously with a well region constituting a substrate of the first depletion type MOS transistor.

17. The delay system according to claim 15 , wherein:
the first depletion type MOS transistor is an element formed on a semiconductor chip, and
the resistance element is constituted by an active region formed simultaneously with active regions constituting a source region and a drain reg

Assignees

• Ueda Yuichi
• Mitsumi Electric Co Ltd

Inventors

• Ueda Yuichi

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• G05F1/567 Primary

  for temperature compensation · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title