Charge pump circuit arrangement

Patent metadata

Field	Value
Publication number	US-11329554-B2
Application number	US-201917055903-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	May 17, 2018
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

First claim

We claim:

1. A charge pump circuit arrangement, comprising:
a multitude of capacitors comprising a first group of capacitors and a second group of capacitors;
the first group of capacitors coupled to a terminal for a first clock signal and the second group of capacitors coupled to a terminal for a second clock signal, the first and second clock signals having non-overlapping clock pulses;
switches that connect one of the capacitors to another one of the capacitors;
each one of the capacitors comprising a semiconductor substrate including a deep well doping region of a first conductivity type and a well doping region of a second conductivity type disposed adjacent to the deep well doping region of the first conductivity type, a portion of the capacitors disposed in the semiconductor substrate;
the deep well doping regions of the first group of capacitors controlled by a first control signal that is in phase with the first clock signal and the deep well doping regions of the second group of capacitors controlled by a second control signal that is in phase with the second clock signal.

2. The charge pump circuit arrangement of claim 1 , wherein the first and second control signals are supplied from a node coupled to another portion of one of the capacitors of the first group and from another node coupled to another portion of one of the capacitors of the second group.

3. The charge pump circuit arrangement of claim 2 , wherein the node and the other node are connected to the other capacitor portions of adjacent capacitors connected to one of the switches.

4. The charge pump circuit arrangement of claim 3 , wherein the capacitors are disposed in a sequence, the sequence comprising a first capacitor connected to a terminal for a supply voltage and a last capacitor connected to a terminal for an output voltage having a voltage higher than the supply voltage, wherein the other node is coupled to the last capacitor and the node is coupled to the capacitor connected to the last capacitor through one of the switches.

5. The charge pump circuit arrangement of claim 1 , wherein the deep well doping regions of the capacitors of the first group are coupled to a switch circuit that is controlled by the first clock signal and that is connected to adjacent capacitors of the sequence of capacitors and the deep well doping regions of the second group of capacitors are coupled to another switch circuit that is controlled by the second clock signal and that is connected to said adjacent capacitors.

6. The charge pump circuit arrangement of claim 5 , wherein the switch circuit and the other switch circuit each comprise:
a terminal for one of the first and second clock signals,
a series connection of complementary MOS transistors connected to one of the capacitors of the first group and one of the capacitors of the second group.

7. The charge pump circuit arrangement of claim 6 , wherein the switch circuit and the other switch circuit each further comprise:
an inverter connected to the terminal for one of the first and second clock signals;
a first switch transistor connected to one of the complementary MOS transistors and the gate terminals of the complementary MOS transistors and a second switch transistor connected to the one of the complementary MOS transistors and the gate terminal of the first switch transistor;
a bootstrap capacitor connected to the terminal for one of the first and second clock signals and to the gate terminal of the second switch transistor;
another bootstrap capacitor connected to the output of the inverter and to the gate terminal of the first switch transistor.

8. The charge pump circuit arrangement claim 5 , wherein one of the adjacent capacitors is connected to a terminal for an output voltage higher than a supply voltage.

9. The charge pump circuit arrangement of claim 1 , wherein the capacitors are MOS capacitors comprising a first plate disposed in one of the well doping regions, a second plate forming a gate electrode disposed above the first plate and doping regions of the first conductivity type disposed in the well doping regions adjacent to the gate electrodes.

10. The charge pump circuit arrangement of claim 1 , wherein each one of the capacitors comprises a semiconductor substrate of a second conductivity type which includes a deep well doping region of a first conductivity type opposite the second conductivity type and a well doping region of the second conductivity type disposed adjacent to the deep well doping region of the first conductivity type, wherein a portion of the capacitors is disposed in the well doping region of the second conductivity type.

11. The charge pump circuit arrangement of claim 1 , wherein the first conductivity type is n-doped and the second conductivity type is p-doped.

12. The charge pump circuit arrangement of claim 1 , wherein the deep well doping regions of the first group of capacitors form a common first deep well doping region of the first conductivity type and the well doping regions of the first group of capacitors form a common first well doping region of the second conductivity type and wherein the deep well doping regions of the second group of capacitors form a common second deep well doping region of the first conductivity type and the well doping regions of the second group of capacitors form a common second well doping region of the second conductivity type.

13. The charge pump circuit arrangement of claim 1 , comprising:
a p-doped substrate;
a n-doped deep well doping region disposed in the substrate, the n-doped deep well doping region enclosing a corresponding p-doped well doping region disposed in the substrate;
n-doped regions disposed in the p-doped well doping regions, the n-doped regions short-circuited with each other;
gate electrodes disposed between adjacent ones of the n-doped regions, wherein the n-doped regions and the gate electrode form a corresponding MOS capacitor.

14. The charge pump circuit arrangement of claim 1 , comprising a sequence of N capacitors of which:
a 1st capacitor is connected to a terminal for a supply voltage;
a 2nd capacitor is connected to the first capacitor by a switch;
a N−1st capacitor is connected to a N-th capacitor by a switch; and
the N-th capacitor is connected to a terminal for an elevated output voltage,
wherein the 1st and the N−1st capacitors are controlled by the first clock signal, the 2nd and the N-th capacitors are controlled by the second clock signal, the deep well doping regions of the 1st and N−1st capacitors are controlled by the first control signal and the deep well doping regions of the 2nd and the N-th capacitor are controlled by the second control signal.

15. The charge pump circuit arrangement of claim 14 , further comprising:
a switch circuit connected to the N−1st and the N-th capacitor and having a terminal for the first clock signal, the switch circuit configured to generate the first control signal; and
another switch circuit connected to the N−1st and the N-th capacitor and having a terminal for the second clock signal, the switch circuit configured to generate the second control signal.

16. The charge pump circuit arrangement of claim 1 , wherein the deep well doping regions of the capacitors of the first group are coupled to a switch circuit that is controlled by the first clock signal and that is connected to one of the capacitors of the first group and one of the capacitors of the second group and the deep well doping regions of the second group of capacitors are coupled to another switch circuit that is controlled by the second clock signa

Assignees

• Ams Ag

Inventors

• Lilic Nenad
• Kappel Robert
• Röhrer Georg

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D1/62

  Capacitors having potential barriers · CPC title

• H10D84/0156

  Manufacturing their doped wells · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title