Method for manufacturing a magnetic random-access memory device using post pillar formation annealing

Patent metadata

Field	Value
Publication number	US-11329217-B2
Application number	US-201916259791-A
Country	US
Kind code	B2
Filing date	Jan 28, 2019
Priority date	Jan 28, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

First claim

What is claimed is:

1. A method for manufacturing a magnetic memory device, the method comprising:
forming CMOS circuitry;
after forming the CMOS circuitry, depositing a series of magnetic memory element layers, the series of magnetic memory element layers including a non-magnetic barrier layer located between first and second magnetic layers;
forming a mask structure over the series of magnetic memory element layers, the mask structure being configured to define an array of memory element pillars;
performing a material removal process to remove portions of the series of magnetic memory layers that are not protected by the mask structure to form an array of pillars;
depositing a dielectric isolation layer around the formed array of pillars by depositing a dielectric isolation material in space where the portions of the series of magnetic memory layers are removed; and
after performing the material removal process and after depositing the dielectric isolation layer, performing a thermal annealing process that is configured to simultaneously anneal the non-magnetic barrier layer to form a desired grain structure in the non-magnetic barrier layer and also to perform back end of line annealing for the CMOS circuitry,
wherein the series of magnetic memory element layers and the dielectric isolation material are deposited over a wafer, and wherein the thermal annealing process further comprises raising the wafer to a temperature of 350 degrees C. to 450 degrees C. within a period of 30-50 minutes and maintaining the wafer at that temperature for a duration of about 40-100 minutes.

2. The method as in claim 1 , wherein no thermal annealing is performed prior to performing the material removal process and depositing the dielectric isolation material.

3. The method as in claim 1 , wherein raising the wafer to a temperature of 350 degrees C. to 450 degrees C. comprises heating the wafer to a temperature of about 400 degrees C.

4. The method as in claim 1 , wherein raising the wafer to a temperature of 350 degrees C. to 450 degrees C. within a period of 30-50 minutes and maintaining the wafer at that temperature for a duration of about 40-100 minutes comprises raising the wafer to a temperature of about 400 degrees C. within a period of about 40 minutes and maintaining the wafer at that temperature for a duration of about 60 minutes.

5. The method as in claim 1 , wherein maintaining the wafer at that temperature for a duration of about 40-100 minutes comprises maintaining that temperature for a duration of about 100 minutes.

6. The method as in claim 1 , wherein raising the wafer to a temperature of 350 degrees C. to 450 degrees C. within a period of 30-50 minutes and maintaining the wafer at that temperature for a duration of about 40-100 minutes comprises heating the wafer to a temperature of about 400 degrees C. for a duration of about 60 minutes in a vacuum.

7. The method as in claim 1 , wherein raising the wafer to a temperature of 350 degrees C. to 450 degrees C. within a period of 30-50 minutes and maintaining the wafer at that temperature for a duration of about 40-100 minutes comprises heating the wafer to a temperature of about 400 degrees C. for a duration of about 60 minutes in a vacuum of about 1×10 −4 Torr.

8. The method as in claim 1 , wherein:
the non-magnetic barrier layer comprises MgO; and
the series of magnetic element layers further comprise a cap layer that includes MgO, and wherein the barrier layer and cap layer are configured to define a resistance ratio (RA barrier/RA cap) that allows for desired performance parameters to be met.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Vasquez Jorge
• KARDASZ Bartlomiej Adam
• Hernandez Jacob Anthony
• Boone Thomas D
• Wolf Georg
• Pinarbasi Mustafa

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01F10/3286

  Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy · CPC title

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title