Self-aligned gate endcap (SAGE) architecture having endcap plugs

Patent metadata

Field	Value
Publication number	US-11329138-B2
Application number	US-201815943552-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a plurality of semiconductor fins protruding through a trench isolation region above a substrate;
a first gate structure over a first of the plurality of semiconductor fins;
a second gate structure over a second of the plurality of semiconductor fins;
a first gate endcap isolation structure laterally between and in contact with the first gate structure and the second gate structure, the first gate endcap isolation structure on the trench isolation region and having an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure; and
a second gate endcap isolation structure laterally between and in contact with first and second lateral portions of the first gate structure, the second gate endcap isolation structure on the trench isolation region and having an uppermost surface below an uppermost surface of the first gate structure, a portion of the first gate structure on the uppermost surface of the second gate endcap isolation structure.

2. The integrated circuit structure of claim 1 , wherein one or both of the first gate endcap isolation structure and the second gate endcap isolation structure comprises an upper dielectric layer on a lower dielectric layer, the upper dielectric layer having a greater dielectric constant than the lower dielectric layer.

3. The integrated circuit structure of claim 1 , wherein one or both of the first gate endcap isolation structure and the second gate endcap isolation structure comprises a centered vertical seam.

4. The integrated circuit structure of claim 1 , wherein the first gate endcap isolation structure is wider than the second gate endcap isolation structure.

5. The integrated circuit structure of claim 1 , wherein the second gate endcap isolation structure is wider than the first gate endcap isolation structure.

6. The integrated circuit structure of claim 1 , wherein the uppermost surface of the first gate endcap isolation structure is co-planar with an uppermost surface of a dielectric cap of each of the first gate structure and the second gate structure.

7. An integrated circuit structure, comprising:
a plurality of semiconductor fins protruding through a trench isolation region above a substrate;
a first source or drain contact structure over a first of the plurality of semiconductor fins; a second source or drain contact structure over a second of the plurality of semiconductor fins;
a first gate endcap isolation structure laterally between and in contact with the first source or drain contact structure and the second source or drain contact structure, the first gate endcap isolation structure on the trench isolation region and having an uppermost surface co-planar with an uppermost surface of the first source or drain contact structure and the second source or drain contact structure; and
a second gate endcap isolation structure laterally between and in contact with first and second lateral portions of the first source or drain contact structure, the second gate endcap isolation structure on the trench isolation region and having an uppermost surface below an uppermost surface of the first source or drain contact structure, a portion of the first source or drain contact structure on the uppermost surface of the second gate endcap isolation structure.

8. The integrated circuit structure of claim 7 , wherein one or both of the first gate endcap isolation structure and the second gate endcap isolation structure comprises an upper dielectric layer on a lower dielectric layer, the upper dielectric layer having a greater dielectric constant than the lower dielectric layer.

9. The integrated circuit structure of claim 7 , wherein one or both of the first gate endcap isolation structure and the second gate endcap isolation structure comprises a centered vertical seam.

10. The integrated circuit structure of claim 7 , wherein the first gate endcap isolation structure is wider than the second gate endcap isolation structure.

11. The integrated circuit structure of claim 7 , wherein the second gate endcap isolation structure is wider than the first gate endcap isolation structure.

12. The integrated circuit structure of claim 7 , wherein the uppermost surface of the first gate endcap isolation structure is co-planar with a conductive surface of each of the first source or drain contact structure and the second source or drain contact structure.

13. An integrated circuit structure, comprising:
a plurality of semiconductor fins protruding through a trench isolation region above a substrate; a first gate structure over a first of the plurality of semiconductor fins;
a second gate structure over the first of the plurality of semiconductor fins; and
a gate endcap isolation structure in contact with the first gate structure and the second gate structure, the gate endcap isolation structure on the trench isolation region and having a first upper surface co-planar with an uppermost surface of the first gate structure, and the gate endcap isolation structure having a second upper surface below the first upper surface, a portion of the second gate structure on the second upper surface of the gate endcap isolation structure.

14. The integrated circuit structure of claim 13 , wherein the gate endcap isolation structure comprises an upper dielectric layer on a lower dielectric layer, the upper dielectric layer having a greater dielectric constant than the lower dielectric layer.

15. The integrated circuit structure of claim 13 , wherein the gate endcap isolation structure comprises a centered vertical seam.

16. The integrated circuit structure of claim 13 , wherein the first upper surface of the gate endcap isolation structure is co-planar with an uppermost surface of a dielectric cap of the first gate structure.

17. An integrated circuit structure, comprising:
a plurality of semiconductor fins protruding through a trench isolation region above a substrate;
a first source or drain contact structure over a first of the plurality of semiconductor fins;
a second source or drain contact structure over the first of the plurality of semiconductor fins; and
a gate endcap isolation structure in contact with the first source or drain contact structure and the second source or drain contact structure, the gate endcap isolation structure on the trench isolation region and having a first upper surface co-planar with an uppermost surface of the first source or drain contact structure, and the gate endcap isolation structure having a recess, the recess having a second upper surface below the first upper surface, a portion of the second source or drain contact structure on the second upper surface of the recess of the gate endcap isolation structure.

18. The integrated circuit structure of claim 17 , wherein the gate endcap isolation structure comprises an upper dielectric layer on a lower dielectric layer, the upper dielectric layer having a greater dielectric constant than the lower dielectric layer.

19. The integrated circuit structure of claim 17 , wherein the gate endcap isolation structure comprises a centered vertical seam.

20. The integrated circuit structure of claim 17 , wherein the first upper surface of the gate endcap isolation structure is co-planar with a conductive surface of the first source or drain contact structure.

Assignees

• Intel Corp

Inventors

• Subramanian Sairam
• Kenyon Christopher
• Govindaraju Sridhar
• Jan Chia-Hong
• Liu Mark
• Liao Szuya S
• Hafez Walid M

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/853

  comprising FinFETs · CPC title