Thin-film transistor embedded dynamic random-access memory with shallow bitline

Patent metadata

Field	Value
Publication number	US-11329047-B2
Application number	US-201815956379-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	Apr 18, 2018
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

First claim

The invention claimed is:

1. An integrated circuit (IC) device, comprising:
a thin-film transistor (TFT) over a substrate, the TFT comprising a channel layer, a gate electrode, a first source/drain (S/D) electrode, and a second S/D electrode, wherein the gate electrode is between the substrate and the channel layer, and the channel layer is between the gate electrode and the first and second S/D electrodes;
a capacitor coupled to the first S/D electrode;
a wordline coupled to the gate electrode;
an insulating layer, the insulating layer including a bitline coupled to the second S/D electrode, and further including an electrically conductive line; and
a bridge via to electrically couple the bitline and the electrically conductive line, where an electrically conductive material of the bridge via fills a gap between the bitline and the electrically conductive line.

2. The IC device according to claim 1 , wherein:
the wordline is between the substrate and the gate electrode, and
the bitline is further away from the substrate than the channel layer.

3. The IC device according to claim 1 , wherein a thickness of the bitline is between 5 and 80 nanometers.

4. The IC device according to claim 1 , wherein a thickness of the bitline is at least 30% smaller than a thickness of the electrically conductive line in the insulating layer.

5. The IC device according to claim 1 , wherein:
the IC device further includes a storage node,
the capacitor is coupled to the first S/D electrode by having a bottom electrode of the capacitor being coupled to the storage node and the storage node being coupled to the first S/D electrode,
the capacitor further includes a top electrode coupled to a capacitor plate, and an insulator between the bottom electrode and the top electrode.

6. The IC device according to claim 5 , wherein:
the bitline is included in a first insulating layer that further includes a first metal layer,
the capacitor is included in a second insulating layer, and
the IC device further includes a capacitor plate metal layer coupled to the capacitor plate, the capacitor plate metal layer included in a third insulating layer,
where the first insulating layer is between the substrate and the second insulating layer, and the second insulating layer is between the first insulating layer and the third insulating layer.

7. The IC device according to claim 6 , further comprising a through capacitor via coupled to the capacitor plate metal layer and to a second metal layer included in the first insulating layer.

8. The IC device according to claim 7 , wherein the IC device includes a memory array comprising a plurality of memory cells, and wherein the through capacitor via is coupled to the first metal layer at a periphery of the memory array.

9. An integrated circuit (IC) device, comprising:
a substrate;
a plurality of wordlines over the substrate, in a first back end of line (BEOL) layer of the IC device;
a memory array comprising a plurality of memory cells, each memory cell comprising:
a thin-film transistor (TFT) in a second BEOL layer of the IC device, the second BEOL layer being further away from the substrate than the first BEOL layer, and
a capacitor in a third BEOL layer of the IC device, the third BEOL layer being further away from the substrate than the second BEOL layer, and the capacitor comprising a first electrode coupled to a first source or drain (S/D) electrode of the TFT;

one or more interconnects for providing electrical connectivity for the memory array, the one or more interconnects provided further away from the substrate than the capacitors of the plurality of memory cells;
at least one through capacitor via extending between at least one of the one or more interconnects and a landing pad in the second BEOL layer, and coupled to a second electrode of the capacitor of each of two or more memory cells of the plurality of memory cells; and
a plurality of bitlines, where each of the plurality of bitlines is coupled to a second S/D electrode of the TFTs of a different one of the plurality of memory cells, and where each of the plurality of bitlines is coupled to a different one of a plurality of metal interconnects outside of the memory array using a bridge via.

10. The IC device according to claim 9 , wherein the landing pad is outside of the memory array.

11. The IC device according to claim 9 ,
wherein a thickness of one or more of the plurality of bitlines is between 20 and 35 nanometers.

12. The IC device according to claim 9 , wherein a thickness of one or more of the plurality of bitlines is at least 50% smaller than a thickness of the plurality of metal interconnects outside of the memory array.

13. The IC device according to claim 9 , wherein each of the plurality of wordlines is coupled to a gate electrode of the TFT of a different one of the plurality of memory cells.

14. The IC device according to claim 9 , further comprising:
a plurality of logic devices in a front end of line (FEOL) layer of the IC device, where the first BEOL layer is further away from the substrate than the plurality of logic devices.

15. The IC device according to claim 14 , wherein the memory array is above the plurality of logic devices.

16. The IC device according to claim 9 , where the IC device is coupled to a further IC component.

17. The IC device according to claim 16 , wherein the further IC component is one of an interposer, a circuit board, a flexible board, or a package substrate.

18. The IC device according to claim 1 , wherein:
the IC device includes a memory array,
the memory array includes a plurality of memory cells,
an individual one of the plurality of memory cells includes the TFT and the capacitor, and
the bridge via and the electrically conductive line are at a periphery of the memory array.

19. The IC device according to claim 1 , wherein the IC device is a dynamic random-access memory (DRAM) device.

20. The IC device according to claim 1 , wherein the IC device is a computing device that includes an embedded dynamic random-access memory (eDRAM) device, and wherein the eDRAM device includes the TFT, the capacitor, the wordline, the bitline, the insulating layer, and the bridge via.

21. The IC device according to claim 9 , wherein the IC device is a dynamic random-access memory (DRAM) device.

22. The IC device according to claim 9 , wherein the IC device is a computing device that includes an embedded dynamic random-access memory (eDRAM) device, and wherein the eDRAM device includes the substrate, the plurality of wordlines, the memory array, the one or more interconnects, the at least one through capacitor via, and the plurality of bitlines.

23. An integrated circuit (IC) device, comprising:
a front-end of line (FEOL) portion, comprising a plurality of logic devices; and
a back-end of line (BEOL) portion, comprising a capacitor plate and a memory array that includes:
a plurality of memory cells, where an individual memory cell of the plurality of memory cells includes a thin-film transistor (TFT), a storage node, and a capacitor having a first capacitor electrode and a second capacitor electrode, where the first capacitor electrode is coupled to the storage node, the storage node is coupled to a first source/drain (S/D) region of the TFT, and where the second capacitor electrode is coupled to the capacitor plate,
a wordline, coupled to a gate of the TFT, and
a bitline, coupled a second S/D region of the TFT,

Assignees

• Intel Corp

Inventors

• Wang Yih
• Sharma Abhishek A
• Ghani Tahir
• Gardiner Allen B
• Lajoie Travis W
• Wang Pei-Hua
• Ku Chieh-Jen
• Sell Bernhard
• Alzate-Vinasco Juan G
• Lin Blake C

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title