Structure and formation method for chip package

Patent metadata

Field	Value
Publication number	US-11329031-B2
Application number	US-202016995062-A
Country	US
Kind code	B2
Filing date	Aug 17, 2020
Priority date	Oct 13, 2015
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

First claim

What is claimed is:

1. A method comprising:
forming a conductive feature over a carrier substrate, sidewalls of the conductive feature having a surface morphology;
heating the conductive feature to increase undulation of the surface morphology, wherein heating the conductive feature forms an interfacial layer on the sidewalls of the conductive feature;
disposing a semiconductor die adjacent the conductive feature over the carrier substrate; and
forming a molding compound encapsulating the interfacial layer and the semiconductor die.

2. The method of claim 1 , wherein the surface morphology of the sidewalls of the conductive feature is the same before and after forming the molding compound.

3. The method of claim 1 further comprising:
forming a redistribution structure comprising redistribution layers electrically connecting the conductive feature and the semiconductor die, wherein the surface morphology of the sidewalls of the conductive feature is the same before and after forming the redistribution structure.

4. The method of claim 3 further comprising:
forming external connectors electrically connected to the redistribution layers of the redistribution structure, wherein the surface morphology of the sidewalls of the conductive feature is the same before and after forming the external connectors.

5. The method of claim 1 , wherein heating the conductive feature is performed at a temperature of from 200° C. to 400° C.

6. The method of claim 1 , wherein heating the conductive feature is performed for a time span of from 30 minutes to 2 hours.

7. The method of claim 1 , wherein heating the conductive feature is performed in a nitrogen-containing and oxygen-containing environment having an oxygen concentration of from 20 ppm to 100 ppm.

8. The method of claim 1 , wherein the molding compound and the interfacial layer have an undulating interface.

9. The method of claim 1 , wherein forming the molding compound forms at least one gap between the molding compound and the interfacial layer.

10. A device comprising:
a semiconductor die;
a molding compound encapsulating the semiconductor die; and
a conductive via extending through the molding compound, the conductive via comprising:
a seed element comprising a first metal;
a conductive feature on the seed element, the conductive feature comprising a second metal, the second metal different from the first metal; and
an interfacial layer surrounding the seed element and the conductive feature, the interfacial layer comprising a first oxide of the first metal and a second oxide of the second metal, an interface of the interfacial layer and the molding compound having an undulate morphology.

11. The device of claim 10 , wherein the first metal is titanium and the second metal is copper.

12. The device of claim 10 , wherein an interface of the interfacial layer and each of the conductive feature and the seed element has an undulate morphology.

13. The device of claim 10 further comprising a gap between the molding compound and the interfacial layer.

14. The device of claim 13 , wherein the undulate morphology has a height variation, and a width of the gap is less than the height variation.

15. A device comprising:
a semiconductor die;
a molding compound encapsulating the semiconductor die;
a conductive feature extending through the molding compound, the conductive feature comprising a first metal; and
an interfacial layer between the conductive feature and the molding compound, the interfacial layer comprising an oxide of the first metal, the conductive feature and the interfacial layer forming a first interface having a first undulating shape with a first height variation, the interfacial layer and the molding compound forming a second interface having a second undulating shape with a second height variation.

16. The device of claim 15 , wherein the first height variation equals the second height variation.

17. The device of claim 15 , wherein the first height variation and the second height variation are each in a range of 10 nm to 130 nm.

18. The device of claim 15 further comprising:
a redistribution structure comprising redistribution layers electrically connecting the conductive feature and the semiconductor die.

19. The device of claim 15 further comprising a gap between the molding compound and the interfacial layer.

20. The device of claim 19 , wherein a width of the gap is less than the first height variation and the second height variation.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Jui-Pin
• Huang Cheng-Lin
• Liu Hsien-Wen
• Jeng Shin-Puu

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title