Intelligent memory device test rack

Patent metadata

Field	Value
Publication number	US-11328789-B2
Application number	US-201916719707-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Dec 18, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.

First claim

What is claimed is:

1. A test rack comprising:
a plurality of memory device test boards each comprising a plurality of memory device test resources, wherein each of the plurality of memory device test boards comprise a separate processing device allocated to the plurality of memory device test resources of a corresponding memory device test board, and wherein each of the plurality of memory device test resources comprise one or more separate test condition components, and wherein the separate processing device of each of the plurality of memory device test boards is to perform operations comprising:
detecting that one or more input/output (IO) components of a first memory sub-system have engaged with one or more corresponding IO components of a first memory device test resource of the plurality of memory device test resources of the corresponding memory device test board, wherein the first memory sub-system comprises a first memory sub-system controller and a first memory device;
identifying a first test to be performed for the first memory device of the first memory sub-system, wherein the first test comprises a set of first test instructions to be executed in performance of the first test, and wherein one or more instructions of the set of first test instructions are to cause one or more first test condition components of the first memory device test resource to generate a first test condition to be applied to the first memory sub-system while the first test is performed at the first memory device; and
causing one or more instructions of the set of first test instructions to be transmitted to the first memory sub-system controller at the first memory sub-system via the one or more of the IO components of the first memory device test resource, wherein the first memory sub-system controller is to perform the first test by executing the one or more instructions of the set of first test instructions for the first memory device at the first memory sub-system.

2. The test rack of claim 1 , wherein the separate processing device of each of the plurality of memory device test boards is to perform operations further comprising:
detecting that a second memory sub-system has engaged with a second memory device test resource of the plurality of memory device test resources of the corresponding memory device test board, wherein the second memory sub-system comprises a second memory sub-system controller and a second memory device;
identifying a second test to be performed for the second memory device of the second memory sub-system, wherein the second test comprises a set of second test instructions to be executed in performance of the second test, and wherein one or more of the set of second test instructions correspond to causing one or more second test condition components of the second memory device test resource to generate a second test condition to be applied to the second memory sub-system during performance of the first test;
causing one or more instructions of the set of second test instructions to be transmitted from the second memory device test resource to the second memory sub-system controller at the second memory sub-system; and
transmitting a first signal to the first memory sub-system controller and a second signal to the second memory sub-system controller, wherein the first signal and the second signal cause the first memory sub-system controller to execute the one or more instructions of the set of first test instructions and the second memory sub-system to execute the one or more instructions of the set of second test instructions simultaneously.

3. The test rack of claim 1 , wherein the processing device of each of the plurality of memory device test boards is to perform operations further comprising:
receiving, from the first memory sub-system, a first set of test results for the first test performed for the first memory device.

4. The test rack of claim 1 , wherein the one or more IO components of the first memory device test resource comprise a first set of serial input/output (IO) pins configured to couple to corresponding serial IO receptacles of the first memory sub-system and a second set of IO pins configured to couple to corresponding non-serial IO receptacles of the first memory sub-system, and wherein the one or more instructions of the set of first test instructions are transmitted to the first memory sub-system controller via the first set of serial IO pins.

5. The test rack of claim 1 , wherein the processing device of each of the plurality of memory device test boards is to perform operations further comprising:
responsive to the one or more first test condition components generating the first test condition during the performance of the first test, receiving, from a test resource monitoring component of the first memory device test resource, data associated with one or more conditions within the first memory device test resource, wherein the one or more conditions correspond to the generated first test condition.

6. The test rack of claim 5 , wherein one or more additional instructions of the set of first test instructions are to cause the one or more first test condition components to generate a second test condition to be applied to the first memory sub-system while the first test is performed at the first memory device, and wherein the operations further comprise:
responsive to the one or more first test condition components generating the second test condition applied to the first memory sub-system during the performance of the first test, receiving, from the test resource monitoring component, additional data associated with the one or more conditions within the first memory device test resource, wherein the one or more conditions correspond to the generated second test condition.

7. The test rack of claim 5 , wherein the one or more first test condition components comprise at least one of a temperature controller or a voltage controller and the test resource monitoring component comprises at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

8. A system comprising:
a memory device; and
a processing device operatively coupled to the memory device, the processing device to perform operations comprising:
receiving, from a requestor, a first request for a test to be performed for a memory sub-system at a memory device test rack, wherein a memory sub-system controller of the memory sub-system is to execute one or more instructions of a set of test instructions for the memory device in performance of the test, and wherein the memory device test rack comprises a plurality of memory device test boards each comprising a plurality of memory device test resources, and wherein each of the plurality of memory device test boards comprises a separate processing device allocated to the memory device test resources of a corresponding memory device test board, and wherein each of the plurality of memory device test resources comprise one or more separate test condition components;
transmitting a second request to each separate processing device to determine which of the plurality of memory device test resources of the corresponding memory device test board are available to facilitate a performance of the test for the memory sub-system;
receiving a response from each separate processing device, the response comprising an indication of whether each of the plurality of memory device test resources of the corresponding memory device test board are available to facilitate the performance of the test;
determining, based on the response received from each separate processing device, an available memory device test resource of the memory device test

Assignees

• Micron Technology Inc

Inventors

• Hamor Gary D
• Spica Michael R
• Shepard Donald
• Caraher Patrick
• Elmiro Da Rocha Chaves João

Classifications

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/56 Primary

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C29/56016 Primary

  Apparatus features · CPC title

• G11C2029/5602

  Interface to device under test · CPC title