Shift register unit and driving method thereof, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-11328672-B2
Application number	US-202016765565-A
Country	US
Kind code	B2
Filing date	Jan 8, 2020
Priority date	Feb 25, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. The shift register unit includes: a first input circuit, a second input circuit, an output circuit, and a compensation circuit, the first input circuit is configured to write a first input signal to the first node in response to a first control signal; the second input circuit is configured to input a second input signal to the second node in response to a detection control signal and configured to transmit a level of the second node to the first node in response to a second control signal; the compensation circuit is configured to compensate the level of the second node; and the output circuit is configured to output a composite output signal to the output terminal under control of a level of the first node.

First claim

What is claimed is:

1. A shift register unit, comprising: a first input circuit, a second input circuit, an output circuit, and a compensation circuit,
wherein the first input circuit is connected to a first node, and is configured to write a first input signal to the first node in response to a first control signal;
the second input circuit is connected to the first node and a second node, and is configured to input a second input signal to the second node in response to a detection control signal and configured to transmit a level of the second node to the first node in response to a second control signal;
the compensation circuit is connected to the second node, and is configured to compensate the level of the second node; and
the output circuit is connected to the first node and an output terminal, and is configured to output a composite output signal to the output terminal under control of a level of the first node;
the compensation circuit comprises a first compensation sub-circuit, a second compensation sub-circuit, and a storage sub-circuit,
the first compensation sub-circuit is connected to the second node and a third node, respectively, and is configured to write a first clock signal to the third node under control of the level of the second node;
the storage sub-circuit is connected to the second node and the third node, respectively, and is configured to compensate the level of the second node based on the first clock signal written to the third node; and
the second compensation sub-circuit is connected to the third node, and is configured to perform noise reduction on the third node under control of a compensation noise reduction signal.

2. The shift register unit according to claim 1 , wherein the second compensation sub-circuit is further connected to a fourth node to receive a voltage of the fourth node as the compensation noise reduction signal.

3. The shift register unit according to claim 2 , wherein the first compensation sub-circuit comprises a first compensation transistor, the second compensation sub-circuit comprises a second compensation transistor, the storage sub-circuit comprises a first capacitor,
a first electrode of the first compensation transistor is connected to a first clock signal terminal to receive the first clock signal, a second electrode of the first compensation transistor is connected to the third node, a gate electrode of the first compensation transistor is connected to the second node,
a first terminal of the first capacitor is connected to the second node, a second terminal of the first capacitor is connected to the third node,
a first electrode of the second compensation transistor is connected to the third node, a second electrode of the second compensation transistor is connected to a first voltage terminal, and a gate electrode of the second compensation transistor is connected to the fourth node.

4. The shift register unit according to claim 1 , wherein the second input circuit comprises a charging sub-circuit and an isolation sub-circuit,
the charging sub-circuit is configured to input the second input signal to the second node in response to the detection control signal; and
the isolation sub-circuit is connected to the first node and the second node, respectively, and is configured to transmit the level of the second node to the first node under control of the second control signal.

5. The shift register unit according to claim 4 , wherein the charging sub-circuit comprises a first transistor, a gate electrode of the first transistor is configured to receive the detection control signal, a first electrode of the first transistor is configured to receive the second input signal, and a second electrode of the first transistor is connected to the second node; and
the isolation sub-circuit comprises a second transistor, a gate electrode of the second transistor is configured to receive the second control signal, a first electrode of the second transistor is connected to the second node, and a second electrode of the second transistor is connected to the first node.

6. The shift register unit according to claim 1 , wherein the output terminal comprises a shift signal output terminal and a first scanning signal output terminal,
the output circuit comprises a first output transistor, a second output transistor, and a second capacitor;
a gate electrode of the first output transistor is connected to the first node, a first electrode of the first output transistor is connected to a first output clock signal terminal to receive a first output clock signal, and a second electrode of the first output transistor is connected to the shift signal output terminal;
a gate electrode of the second output transistor is connected to the first node, a first electrode of the second output transistor is connected to the first output clock signal terminal to receive the first output clock signal, and a second electrode of the second output transistor is connected to the first scanning signal output terminal;
a first terminal of the second capacitor is connected to the first node, and a second terminal of the second capacitor is connected to the second electrode of the second output transistor; and
the first output clock signal is transmitted to the shift signal output terminal via the first output transistor and serves as a first output signal, the first output clock signal is transmitted to the first scanning signal output terminal via the second output transistor and serves as a second output signal, and the composite output signal comprises the first output signal and the second output signal.

7. The shift register unit according to claim 6 , wherein the output terminal further comprises a second scanning signal output terminal, and the output circuit further comprises a third output transistor and a third capacitor,
a gate electrode of the third output transistor is connected to the first node, a first electrode of the third output transistor is connected to a second output clock signal terminal to receive a second output clock signal, a second electrode of the third output transistor is connected to the second scanning signal output terminal,
a first terminal of the third capacitor is connected to the first node, a second terminal of the third capacitor is connected to the second electrode of the third output transistor, and
the second output clock signal is transmitted to the second scanning signal output terminal via the third output transistor and serves as a third output signal, and the composite output signal further comprises the third output signal.

8. The shift register unit according to claim 1 , further comprising a noise reduction circuit and a first control circuit,
wherein the noise reduction circuit is connected to the first node, a fourth node, and the output terminal, and is configured to simultaneously perform noise reduction on the first node and the output terminal under control of a level of the fourth node; and
the first control circuit is connected to the first node and the fourth node, and is configured to control the level of the fourth node under control of the level of the first node.

9. The shift register unit according to claim 1 , further comprising: a second control circuit,
wherein the second control circuit is connected to a fourth node, and is configured to control a level of the fourth node in response to a third control signal, and the third control signal comprises a first clock signal and a voltage of the second node.

10. The shift register unit according to claim 1 , further comprising a first reset circuit and a second reset circuit,
wherein the first reset circuit is connected to the first node, and is configured to re

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Feng Xuehuan
• Li Yongqian

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3225

  using an active matrix · CPC title