Shift register unit, driving method thereof, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-11328641-B2
Application number	US-202016839413-A
Country	US
Kind code	B2
Filing date	Apr 3, 2020
Priority date	Nov 27, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A shift register unit, a driving method thereof, a gate driving circuit, and a display device are provided. The shift register unit includes an input branch and a reset branch; the input branch is configured to form or disconnect a first path between a first scan voltage terminal and a pull-up node under control of a potential of a first control terminal. The reset branch is configured to form or disconnect a second path between a second scan voltage terminal and the pull-up node under control of a potential of a second control terminal.

First claim

What is claimed is:

1. A shift register unit, comprising
an input branch; and
a reset branch;
wherein the input branch is configured to form or disconnect a first path between a first scan voltage terminal and a pull-up node under control of a potential of a first control terminal,
wherein the reset branch is configured to form or disconnect a second path between a second scan voltage terminal and the pull-up node under control of a potential of a second control terminal, and
wherein the shift register unit further comprises at least one of:
a switch circuit, wherein the switch circuit is configured to: under control of a switch control signal provided by a switch control line, control a connection between an input terminal and the first control terminal to be turned on and control a connection between a reset terminal and the second control terminal to be turned on; or
a pull-up node control circuit, wherein the pull-up node control circuit is configured to control the pull-up node to be electrically connected to the first scan voltage terminal under control of an input signal provided by an input terminal, and to control the pull-up node to be electrically connected to the second scan voltage terminal under control of a reset signal provided by a reset terminal; or
a pull-down node control circuit, a pull-up node reset circuit, a storage capacitor, and an output circuit, wherein the pull-down node control circuit is configured to control a potential of a pull-down node under control of the pull-up node, the pull-up node reset circuit is configured to reset a potential of the pull-up node under control of the pull-down node, a first terminal of the storage capacitor is electrically connected to the pull-up node, a second terminal of the storage capacitor is electrically connected to a gate driving signal output terminal, and the output circuit is configured to control the gate driving signal output terminal to output a gate driving signal under control of the potential of the pull-up node and the potential of the pull-down node.

2. The shift register unit according to claim 1 , wherein the input branch comprises at least one auxiliary input transistor; and
wherein a control electrode of the auxiliary input transistor is electrically connected to the first control terminal, a first electrode of the auxiliary input transistor is electrically connected to the first scan voltage terminal, and a second electrode of the auxiliary input transistor is electrically connected to the pull-up node.

3. The shift register unit according to claim 1 , wherein the reset branch comprises at least one auxiliary reset transistor; and
wherein a control electrode of the auxiliary reset transistor is electrically connected to the second control terminal, a first electrode of the auxiliary reset transistor is electrically connected to the pull-up node, and a second electrode of the auxiliary reset transistor is electrically connected to the second scan voltage terminal.

4. The shift register unit according to claim 1 wherein the switch circuit comprises a first switch transistor and a second switch transistor;
wherein a control electrode of the first switch transistor is electrically connected to the switch control line, a first electrode of the first switch transistor is electrically connected to the input terminal, and a second electrode of the first switch transistor is electrically connected to the first control terminal; and
wherein a control electrode of the second switch transistor is electrically connected to the switch control line, a first electrode of the second switch transistor is electrically connected to the reset terminal, and a second electrode of the second switch transistor is electrically connected to the second control terminal.

5. The shift register unit according to claim 1 , wherein the pull-up node control circuit comprises an input transistor and a reset transistor;
wherein a control electrode of the input transistor is electrically connected to the input terminal, a first electrode of the input transistor is electrically connected to the first scan voltage terminal, and a second electrode of the input transistor is electrically connected to the pull-up node; and
wherein a control electrode of the reset transistor is electrically connected to the reset terminal, a first electrode of the reset transistor is electrically connected to the pull-up node, and a second electrode of the reset transistor is electrically connected to the second scan voltage terminal.

6. The shift register unit according to claim 2 , wherein the pull-up node control circuit comprises an input transistor and a reset transistor;
wherein a control electrode of the input transistor is electrically connected to the input terminal, a first electrode of the input transistor is electrically connected to the first scan voltage terminal, and a second electrode of the input transistor is electrically connected to the pull-up node; and
wherein a control electrode of the reset transistor is electrically connected to the reset terminal, a first electrode of the reset transistor is electrically connected to the pull-up node, and a second electrode of the reset transistor is electrically connected to the second scan voltage terminal.

7. The shift register unit according to claim 3 , wherein the pull-up node control circuit comprises an input transistor and a reset transistor;
wherein a control electrode of the input transistor is electrically connected to the input terminal, a first electrode of the input transistor is electrically connected to the first scan voltage terminal, and a second electrode of the input transistor is electrically connected to the pull-up node; and
wherein a control electrode of the reset transistor is electrically connected to the reset terminal, a first electrode of the reset transistor is electrically connected to the pull-up node, and a second electrode of the reset transistor is electrically connected to the second scan voltage terminal.

8. The shift register unit according to claim 1 , wherein the pull-down node control circuit comprises:
a first pull-down control transistor, a gate electrode and a drain electrode of which are electrically connected to a first voltage terminal, and a source electrode of which is electrically connected to a first pull-down control node;
a second pull-down control transistor, a gate electrode of which is electrically connected to the pull-up node, a drain electrode of which is electrically connected to the first pull-down control node, and a source electrode of which is electrically connected to a low voltage terminal, wherein the low voltage terminal is configured to provide a low voltage;
a third pull-down control transistor, a gate electrode of which is electrically connected to the first pull-down control node, a drain electrode of which is electrically connected to the first voltage terminal, and a source electrode of which is electrically connected to the first pull-down node;
a fourth pull-down control transistor, a gate electrode of which is electrically connected to the pull-up node, a drain electrode of which is electrically connected to the first pull-down node, and a source electrode of which is connected to the low voltage;
a fifth pull-down control transistor, a gate electrode and a drain electrode of which are electrically connected to a second voltage terminal, and a source electrode of which is electrically connected to a second pull-down control node;
a sixth pull-down control transistor, a gate electrode of which is electrically connected to the pull-up node, a drain electrode of which is electrically connected to the second pull-down control node, and a source electrode of which is electrically

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• He Zhiyang
• Zheng Mindong
• Li Youlu
• Xie Yongxian
• Liu Qiang
• Wang Hui

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title