Processor-based system employing local dynamic power management based on controlling performance and operating power consumption, and related methods

Patent metadata

Field	Value
Publication number	US-11327552-B1
Application number	US-202117178041-A
Country	US
Kind code	B1
Filing date	Feb 17, 2021
Priority date	Feb 17, 2021
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

First claim

What is claimed is:

1. A processor-based system configured to receive a power budget to govern its power consumption based on an overall power budget for a plurality of processor-based systems, the processor-based system comprising:
a power circuit configured to set an operating voltage of a power signal based on a power budget and distribute the power signal on a power output;
a power rail coupled to the power output;
a clock circuit configured to generate a clock signal at an operating frequency on a clock output based on the power budget; and
a processing unit comprising at least one compute processor core each coupled to the power rail and the clock output, and each configured to execute program code at a rate based on the operating frequency of the clock signal; and
a power control circuit configured to:
(a) determine a current power consumption of the processor-based system based on the at least one compute processor core operating at a current operating frequency of the clock signal and a current operating voltage of the power signal;
(b) determine if the current power consumption by the processor-based system is greater than the power budget for the processor-based system; and
(c) in response to determining the current power consumption is greater than the power budget:
cause the clock circuit to generate the clock signal at a next operating frequency lower than the current operating frequency;
determine if the current operating frequency of the clock signal is at or lower than the next operating frequency; and
in response to determining the current operating frequency is at or lower than the next operating frequency:
cause the power circuit to generate the power signal at a next operating voltage lower than the current operating voltage.

2. The processor-based system of claim 1 , wherein the power control circuit is further configured to:
determine if the current power consumption by the processor-based system is less than the power budget for the processor-based system; and
in response to determining the current power consumption is less than the power budget:
cause the power circuit to generate the power signal at a next operating voltage higher than the current operating voltage;
determine if the current operating voltage of the power signal is at or higher than the next operating voltage; and
in response to determining the current operating voltage is at or higher than the than the next operating voltage:
cause the clock circuit to generate the clock signal at a next operating frequency higher than the current operating frequency; and

the power control circuit configured to set the operating voltage of the power signal at the next operating voltage.

3. The processor-based system of claim 1 , wherein the power control circuit is further configured to:
determine if the current power consumption by the processor-based system is equal to the power budget for the processor-based system; and
in response to determining the current power consumption is equal to the power budget:
not cause the power circuit to generate the power signal at a next operating voltage different from current operating voltage; and
not cause the clock circuit to generate the clock signal at a next operating frequency different from the current operating frequency.

4. The processor-based system of claim 1 , wherein the power control circuit is configured to repeat steps (a)-(c).

5. The processor-based system of claim 1 , wherein the power control circuit comprises a power control processor configured to execute program code to perform steps (a)-(c).

6. The processor-based system of claim 1 , further comprising a memory comprising a voltage-frequency table comprising a plurality of voltage-frequency pair entries each comprising a voltage level entry configured to store an operating voltage level and a frequency level entry configured to store a corresponding operating frequency level for the operating voltage level.

7. The processor-based system of claim 6 , wherein the power control circuit further configured to:
in response to determining the current power consumption is greater than the power budget:
access the frequency level entry in a voltage-frequency pair entry among the plurality of voltage-frequency pair entries in the voltage-frequency table corresponding to the current operating frequency;
set the next operating frequency to the operating frequency level in the frequency level entry of a next voltage-frequency pair entry among the plurality of voltage-frequency pair entries in the voltage-frequency table having a next lower operating frequency level from the current operating frequency; and
in response to determining the current operating frequency is at or lower than the than the next operating frequency:
set the next operating voltage to the operating voltage level in the voltage level entry of the next voltage-frequency pair entry.

8. The processor-based system of claim 6 , wherein the power control circuit is further configured to:
determine if the current power consumption by the processor-based system is less than the power budget for the processor-based system; and
in response to determining the current power consumption is less than the power budget:
access the voltage level entry in a voltage-frequency pair entry among the plurality of voltage-frequency pair entries in the voltage-frequency table corresponding to the current operating voltage;
set the next operating voltage to the operating voltage level in the voltage level entry of a next voltage-frequency pair entry among the plurality of voltage-frequency pair entries in the voltage-frequency table having a next higher operating voltage level from the current operating voltage; and
cause the power circuit to generate the power signal at the next operating voltage;
determine if the current operating voltage of the power signal is at or higher than the next operating voltage; and
in response to determining the current operating voltage is at or higher than the than the next operating voltage:
set the next operating frequency to the operating frequency level in the operating frequency entry of the next voltage-frequency pair entry; and
cause the clock circuit to generate the clock signal at the next operating frequency.

9. The processor-based system of claim 7 , wherein the power control circuit further configured to change the operating voltage level in voltage level entry and the operating frequency level in the frequency level entry of a voltage-frequency pair entry among the plurality of voltage-frequency pair entries.

10. The processor-based system of claim 1 , wherein:
the power control circuit is configured to cause the clock circuit to generate the clock signal at the next operating frequency lower than the current operating frequency, by being configured to:
communicate a frequency change request comprising the next operating frequency lower to the clock circuit; and

the clock circuit is further configured to:
receive the frequency change request from the power control circuit;
(d) generate the clock signal on the clock output at a next intermediate operating frequency between the current operating frequency and the next operating frequency; and
(e) verify the clock signal at the next intermediate operating frequency;
(f) in response to verifying the clock signal at the next intermediate operating frequency, repeat steps (d)-(e) one or more times until the next intermediate operating frequency is the next operating frequency;
generate the clock signal on the clock output at the next operating frequency; and
communicate a voltage change request comprising the next operating voltage lower

Assignees

• Microsoft Technology Licensing Llc
• Microsoft Licensing Tech Llc

Inventors

• Rapaka Smitha L
• Law Patrick Y
• Mapes Teague C

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title