Circuit and method for capacitance detection, touch chip and electronic device

US11326907B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11326907-B2
Application numberUS-202017009763-A
CountryUS
Kind codeB2
Filing dateSep 1, 2020
Priority dateAug 1, 2019
Publication dateMay 10, 2022
Grant dateMay 10, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit and method for capacitance detection, a touch chip, and an electronic device are provided. The circuit includes a control module, a driving module, an offsetting module, and a charge transfer module, the driving module being configured to positively charge a capacitor to be detected through a first charging branch circuit, or negatively charge the capacitor to be detected through a second charging branch circuit under the control of the control module; the offsetting module being configured to offset base capacitance of the capacitor to be detected through a first offsetting branch circuit under the control of the control module, or offset the base capacitance of the capacitor to be detected through a second offsetting branch circuit under the control of the control module; the charge transfer module being configured to transfer a charge on the capacitor to be detected to generate an output voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit for capacitance detection, comprising: a control module, a driving module, an offsetting module, and a charge transfer module, the driving module being configured to positively charge a capacitor to be detected through a first charging branch circuit; the offsetting module being configured to offset base capacitance of the capacitor to be detected through a first offsetting branch circuit under the control of the control module; the driving module being configured to negatively charge the capacitor to be detected through a second charging branch circuit under the control of the control module; the offsetting module being configured to offset the base capacitance of the capacitor to be detected through a second offsetting branch circuit under the control of the control module; the charge transfer module being configured to transfer a charge on the capacitor to be detected to generate an output voltage. 2. The circuit according to claim 1 , wherein the capacitor to be detected is connected to a positive voltage source through the first charging branch circuit, such that the first charging branch circuit positively charges the capacitor to be detected; and the capacitor to be detected is electrically connected to a negative voltage source through the second charging branch circuit, such that the second charging branch circuit negatively charges the capacitor to be detected. 3. The circuit according to claim 1 , wherein the offsetting module comprises a first offset resistor and a second offset resistor, the offsetting module is connected to a negative voltage source through one terminal of the first offsetting branch circuit, the capacitor to be detected being in a first discharging state through the first offset resistor when the offsetting module offsets the base capacitance of the capacitor to be detected through the first offsetting branch circuit; and the offsetting module is connected to a positive voltage source through one terminal of the second offsetting branch circuit, the capacitor to be detected being in a second discharging state through the second offset resistor when the offsetting module offsets the base capacitance of the capacitor to be detected through the second offsetting branch circuit; wherein a resistance of the first offset resistor is unequal to a resistance of the second offset resistor. 4. The circuit according to claim 1 , wherein the charge transfer module comprises a differential amplifying circuit, an inverting terminal of the differential amplifying circuit is electrically connected to a common mode voltage, and a non-inverting terminal of the differential amplifying circuit is electrically connected to the capacitor to be detected, to transfer the charge on the capacitor to be detected; the non-inverting terminal of the differential amplifying circuit is electrically disconnected from the capacitor to be detected, to charge and offset the capacitor to be detected. 5. The circuit according to claim 1 , before the driving module negatively charge the capacitor to be detected through a second charging branch circuit under the control of the control module, comprising, the charge transfer module transfer a charge on the capacitor to be detected to generate an output voltage. 6. The circuit according to claim 1 , wherein the driving module comprises at least two switch units, and the at least two switch units switch switching states under the control of the control module to form the first charging branch circuit and the second charging branch circuit, respectively. 7. The circuit according to claim 6 , wherein the switch units are single-pole single-throw switch units, and the control module is further configured to control one of the single-pole single-throw switch units to be closed, to form the first charging branch circuit, and control the other of the single-pole single-throw switch units to be closed, to form the second charging branch circuit; or the switch units are single-pole double-throw switch units, and the control module is further configured to control the single-pole double-throw switch units to switch between different contacts to form the first charging branch circuit and the second charging branch circuit. 8. The circuit according to claim 1 , wherein the offsetting module comprises at least two switch units, and the at least two switch units switch switching states under the control of the control module to form the first offsetting branch circuit and the second offsetting branch circuit, respectively. 9. The circuit according to claim 8 , wherein the switch units are single-pole single-throw switch units, and the control module is further configured to control one of the single-pole single-throw switch units to be closed, to form the first offsetting branch circuit, and control the other of the single-pole single-throw switch units to be closed, to form the second offsetting branch circuit; or the switch units are single-pole double-throw switch units, and the control module is further configured to control the single-pole double-throw switch units to switch between different contacts to form the first offsetting branch circuit and the second offsetting branch circuit. 10. A method for capacitance detection, comprising: positively charging, by a driving module, a capacitor to be detected through a first charging branch circuit under the control of a control module; offsetting, by an offsetting module, base capacitance of the capacitor to be detected through a first offsetting branch circuit under the control of the control module; negatively charging, by a driving module, the capacitor to be detected through a second charging branch circuit under the control of a control module; offsetting, by the offsetting module, the base capacitance of the capacitor to be detected through a second offsetting branch circuit under the control of the control module; and transferring, by a charge transfer module, a charge on the capacitor to be detected to generate an output voltage. 11. The method according to claim 10 , wherein when the first charging branch circuit positively charges the capacitor to be detected, the capacitor to be detected is connected to a positive voltage source through the first charging branch circuit; and when the second charging branch circuit negatively charges the capacitor to be detected, the capacitor to be detected is electrically connected to a negative voltage source through the second charging branch circuit. 12. The method according to claim 10 , wherein the offsetting module comprises a first offset resistor and a second offset resistor, the offsetting module is connected to a negative voltage source through one terminal of the first offsetting branch circuit, and the capacitor to be detected being in a first discharging state through the first offset resistor when the offsetting module offsets the base capacitance of the capacitor to be detected through the first offsetting branch circuit; and the offsetting module is connected to a positive voltage source through one terminal of the second offsetting branch circuit, the capacitor to be detected being in a second discharging state through the second offset resistor when the offsetting module offsets the base capacitance of the capacitor to be detected through the second offsetting branch circuit; wherein a resistance of the first offset resistor is unequal to a resistance of the second offset resistor. 13. The method according to claim 10 , wherein the charge transfer module comprises a differential amplifying circuit, an inverting terminal of the differential amplifying circuit is electrically connected to a comm

Assignees

Inventors

Classifications

  • H03K17/962Primary

    Capacitive touch switches · CPC title

  • G01D5/24Primary

    by varying capacitance · CPC title

  • Charge-transfer · CPC title

  • Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title

  • Filtering of noise external to the device and not generated by digitiser components · CPC title

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What does patent US11326907B2 cover?
A circuit and method for capacitance detection, a touch chip, and an electronic device are provided. The circuit includes a control module, a driving module, an offsetting module, and a charge transfer module, the driving module being configured to positively charge a capacitor to be detected through a first charging branch circuit, or negatively charge the capacitor to be detected through a se…
Who is the assignee on this patent?
Shenzhen Goodix Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03K17/962. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 10 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).