High-speed multiplexer

Patent metadata

Field	Value
Publication number	US-11323115-B1
Application number	US-202117316069-A
Country	US
Kind code	B1
Filing date	May 10, 2021
Priority date	May 10, 2021
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A high-speed multiplexor comprises a set of differential input pairs to receive and mix a set of differential input signals at a differential output node pair. The high-speed multiplexer further comprises an active inductive load pair driven by the input stage using the mixed set of differential input signals. Each active inductive load comprises a p-channel field effect transistor (pFET) device connected to one of the differential output node pairs and a resistor connected between a gate node and a drain node of the pFET device. The multiplexer further comprises a first cross-coupling capacitor connected between the gate node of a first inductive load and a second output node of the differential output node pair and a second cross-coupling capacitor connected between the gate node of a second inductive load and a first output node of the differential output node pair.

First claim

What is claimed is:

1. A device comprising:
an input stage comprising a set of differential input pairs to receive a set of differential input signals and provide a differential output signal based on the set of differential input signals at a differential output node pair;
an active inductive load pair connected to the input stage, the active inductive load pair equalizing the differential output signal provided at the differential output node pair, the active inductive load pair comprising:
a first active inductive load connected to a first output node of the differential output node pair;
a second active inductive load connected to a second output node of the differential output node pair;
a first capacitor connected between the second active inductive load and the first output node; and
a second capacitor connected between the first active inductive load and the second output node; and
a first bias control element and a second bias control element, the first bias control element and the second bias control element receiving a first bias voltage at a common gate node, the first bias control element being connected to a first drain node, the second bias control element being connected to a second drain node, the first drain node being connected to a drain of a first p-channel field-effect transistor (pFET) device of the first active inductive load, the second drain node being connected to a drain of a second pFET device of the second active inductive load.

2. The device of claim 1 , wherein:
the first active inductive load comprises:
the first pFET device connected to the first output node; and
a first resistor connected between a first gate node and the first drain node, the first gate node being connected to a gate of the first pFET device;
the second active inductive load comprises:
the second pFET device connected to the second output node; and
a second resistor connected between a second gate node and the second drain node, the second gate node being connected to a gate of the second pFET device.

3. The device of claim 2 , wherein:
the first capacitor is connected between the second gate node and the first output node; and
the second capacitor is connected between the first gate node and the second output node.

4. The device of claim 1 , further comprising a third bias control element and a fourth bias control element, the third bias control element and the fourth bias control element receiving a second bias voltage and being connected to a common ground, the third bias control element being connected to the first gate node, the fourth bias control element being connected to the second gate node.

5. The device of claim 1 , wherein:
each of the first bias control element and second bias control element comprise a pFET device, and
each of the third bias control element and fourth bias control element comprise an nFET device.

6. The device of claim 1 , wherein the input stage generates the differential output signal by mixing the set of differential input signals.

7. The device of claim 1 , wherein a first differential input pair in the set of differential input pairs comprises a pair of n-channel field-effect transistor (nFET) devices connected to a common ground.

8. The device of claim 7 , wherein:
a first nFET device in the pair of nFET devices receives a first input signal, and
a second nFET device in the pair of nFET devices receives an inverse of the first input signal.

9. The device of claim 1 , wherein the active inductive load pair forms a cross-coupled pair at high frequency.

10. A method comprising:
receiving a set of differential input signals at an input stage of a multiplexer;
generating, at a differential output node of the multiplexer, a differential output signal based on the set of differential input signals;
equalizing the differential output signal by driving an active inductive load pair using the differential output signal, the equalizing of the differential output signal resulting in an equalized differential output signal, the active inductive load pair comprising:
a first active inductive load connected to a first output node of the differential output node pair;
a second active inductive load connected to a second output node of the differential output node pair; and
a first bias control element and a second bias control element, the first bias control element and the second bias control element receiving a first bias voltage at a common gate node, the first bias control element being connected to a first drain node, the second bias control element being connected to a second drain node, the first drain node being connected to a drain of a first p-channel field-effect transistor (pFET) device of the first active inductive load, the second drain node being connected to a drain of a second pFET device of the second active inductive load; and
providing the equalized differential output signal at the differential output node of the multiplexer.

11. The method of claim 10 , wherein the generating of the differential output signal comprises mixing the set of differential input signals at the differential output node.

12. The method of claim 10 , wherein the input stage of the multiplexer comprises a set of differential input pairs to receive the set of differential input signals.

13. The method of claim 10 , wherein the first active inductive load is crossed-coupled with thee second inductive load by a first cross-coupling capacitor and a second cross-coupling capacitor.

14. The method of claim 13 , wherein:
the first cross-coupling capacitor is connected between the second active inductive load and the first output node; and
the second cross-coupling capacitor connected between the first active inductive load and the second output node.

15. The method of claim 14 , wherein:
the first active inductive load comprises:
the first pFET device connected to the first output node; and
a first resistor connected between a first gate node and a first drain node, the first gate node being connected to a gate of the first pFET device, the first drain node being connected to a drain of the first pFET device;
the second active inductive load comprises:
the second pFET device connected to the second output node; and
a second resistor connected between a second gate node and a second drain node, the second gate node being connected to a gate of the second pFET device, the second drain node being connected to a drain of the second pFET device.

16. The method of claim 15 , wherein:
the first cross-coupling capacitor is connected between the second gate node and the first output node; and
the second cross-coupling capacitor is connected between the first gate node and the second output node.

17. The method of claim 10 , wherein:
a first differential input pair in the set of differential input pairs comprises a pair of n-channel field-effect transistor (nFET) devices connected to a common ground;
a first nFET device in the pair of nFET devices receives a first input signal; and
a second nFET device in the pair of nFET devices receives an inverse of the first input signal.

18. A system comprising:
a driver; and
a multiplexer comprising a differential output node connected to a driver input of the driver, the multiplexer further comprising:
a set of differential input pairs to receive a set of differential input signals and provide a differential output signal based on the set of differential input signals at the differential output node pair;
an active inductive load pair connected to the

Assignees

• Cadence Design Systems Inc

Inventors

• Yuan Xiaobin
• Loizos Dimitrios
• Joshi Varun

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K17/04123

  in field-effect transistor switches · CPC title

• H03K2017/6878

  using multi-gate field-effect transistors · CPC title

• H03K17/64

  having inductive loads · CPC title

• H03K17/735 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (H03K17/722 takes precedence; logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title