Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11322604-B2
Application number	US-202016928282-A
Country	US
Kind code	B2
Filing date	Jul 14, 2020
Priority date	Sep 25, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate of a first conductive type in which an IGBT region and a diode region are defined in a plan view;
a collector layer of a second conductive type disposed on a back surface side of the semiconductor substrate in the IGBT region;
a base layer of the second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region;
an emitter layer of the first conductive type selectively disposed on the base layer;
a first contact layer of the second conductive type selectively disposed on the base layer and having higher impurity concentration than that of the base layer;
a plurality of first trench electrodes respectively disposed in a plurality of first trenches that reach the semiconductor substrate from the emitter layer through the base layer, with a plurality of first insulating films interposed therebetween;
an emitter electrode electrically connected to the emitter layer and the first contact layer;
a cathode layer of the first conductive type disposed on the back surface side of the semiconductor substrate in the diode region and having higher impurity concentration than that of the semiconductor substrate;
an anode layer of the second conductive type disposed on the front surface side of the semiconductor substrate in the diode region; and
a plurality of second trench electrodes respectively disposed in a plurality of second trenches that reach the semiconductor substrate from the anode layer, with a plurality of second insulating films interposed therebetween, so as to sandwich the anode layer in plan view, wherein
at least any one of the plurality of first trench electrodes is electrically connected to a gate electrode,
each of the plurality of second trench electrodes is electrically connected to the gate electrode or the emitter electrode,
the anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion, and
at least a part of an upper portion of the second portion of the anode layer is covered with the emitter electrode and is electrically connected to the emitter electrode.

2. The semiconductor device according to claim 1 , further comprising
a second contact layer of the second conductive type disposed on the anode layer other than at least the part of the upper portion of the second portion and having higher impurity concentration than that of the anode layer.

3. The semiconductor device according to claim 2 , wherein
a ratio of an area of the second contact layer to a total area of the second contact layer and the anode layer sandwiched between a pair of the second trench electrodes in plan view is 80% or lower.

4. The semiconductor device according to claim 2 , wherein
a ratio of an area of the second contact layer to a total area of the second contact layer and the anode layer sandwiched between a pair of the second trench electrodes in plan view is 30% or higher.

5. A manufacturing method of the semiconductor device according to claim 1 , comprising the steps of:
selectively forming a resist on a front surface of the semiconductor substrate in the diode region;
implanting impurities of the second conductive type into a front surface of the semiconductor substrate in the IGBT region and an exposed portion of the front surface of the semiconductor substrate in the diode region, which is exposed from the resist; and
by performing thermal diffusion treatment, forming the base layer in the IGBT region, forming the first portion in at least a part of a portion into which the impurities are implanted in the diode region, and forming the second portion in a portion adjacent to the at least the part thereof in plan view.

6. The semiconductor device according to claim 1 , wherein
the diode region includes a freewheeling diode.

7. The semiconductor device according to claim 1 , wherein
the first portion and the second portion have respective impurity concentrations equal to or less than the impurity concentration of the base layer.

8. The semiconductor device according to claim 1 , wherein
at least two second portions respectively are positioned adjacent to each of opposite sides of the first portion in plan view.

9. The semiconductor device according to claim 1 , wherein
in cross-sectional view, the lower end of the second portion of the anode layer includes a spiny concave part.

Assignees

• Mitsubishi Electric Corp

Inventors

• Soneda Shinya
• Kamibaba Ryu
• Nitta Tetsuya

Classifications

• H10D62/128

  Anode regions of diodes · CPC title

• H10D84/131

  Thyristors having built-in components · CPC title

• H10D12/032

  of vertical IGBTs · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D8/045

  of PN junction diodes · CPC title