Semiconductor device and memory device
US-9806202-B2 · Oct 31, 2017 · US
US11322527B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11322527-B2 |
| Application number | US-201816096946-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 5, 2018 |
| Priority date | Mar 13, 2018 |
| Publication date | May 3, 2022 |
| Grant date | May 3, 2022 |
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The present invention teaches a pixel unit including thin film transistors (TFTs) and pixel electrodes corresponding to the TFTs. The pixel electrodes are connected to the source electrodes of the TFTs. Each pixel electrode includes multiple arc-shaped electrode units arranged at intervals along an axial direction around a periphery of a corresponding TFT. The electrode units are electrically connected together. The present invention adopts arc-shaped pixels (similar to concentric circles) so that liquid crystal molecules are closer to being isotropic. Then, by having different vertical alignment (VA) TFT designs in the primary pixel region and secondary pixel region and utilizing the differences in W/L and capacitance, different voltage levels for primary pixel electrode and secondary pixel electrode are achieved. The color shift problem is improved and the viewing angle is enhanced.
Opening claim text (preview).
What is claimed is: 1. A pixel unit, comprising thin film transistors (TFTs) and pixel electrodes corresponding to the TFTs, wherein the pixel electrodes are connected to the source electrodes of the TFTs; each pixel electrode comprises multiple arc-shaped electrode units arranged at intervals along an axial direction around a periphery of a corresponding TFT; and the electrode units are electrically connected together; wherein the TFTs of the pixel unit are TFTs using vertical alignment (VA); each TFT comprises a gate electrode, a source electrode, an active layer, and a drain electrode; the source electrode and the gate electrode have non-overlapping projections along a vertical direction; and the drain electrode and the gate electrode have non-overlapping projections along the vertical direction; wherein the source electrode, the active layer, and the drain electrode of a TFT are arranged around the periphery of the gate electrode; the source electrode, the active layer, and the drain electrode are stacked; and the electrode units are arranged at intervals along an axial direction with the gate electrode as center. 2. The pixel unit according to claim 1 , further comprising scan lines, a data line, and a primary pixel region and a secondary pixel region jointly defined by the scan lines and the data line. 3. The pixel unit according to claim 2 , wherein the arc-shaped electrode units have their mouths facing a center of a corresponding TFT; and each electrode unit has a second end electrically connected to a first end of an axially neighboring electrode unit. 4. The pixel unit according to claim 2 , wherein the arc-shaped electrode units have their mouths facing outward away from a center of a corresponding TFT. 5. The pixel unit according to claim 2 , wherein the drain electrode of a TFT comprises an arc-shaped first drain electrode and an arc-shaped second drain electrode; the first and second drain electrodes have their mouths facing each other, and are electrically connected to the data line respectively through a branch line; and the gate electrode is a part of a scan line, and is located in an area circled by the first and second drain electrode. 6. The pixel unit according to claim 2 , wherein the drain electrode of a TFT comprises four arc-shaped drain electrode units with their mouths facing outward away from the gate electrode; the drain electrode units are a part of the data line, and are end-to-end connected to enclose an area; and the gate electrode is configured inside the enclosed area, and is part of a scan line. 7. The pixel unit according to claim 1 , wherein the arc-shaped electrode units have their mouths facing a center of a corresponding TFT; and each electrode unit has a second end electrically connected to a first end of an axially neighboring electrode unit. 8. The pixel unit according to claim 1 , wherein the arc-shaped electrode units have their mouths facing outward away from a center of a corresponding TFT. 9. The pixel unit according to claim 1 , wherein the drain electrode of a TFT comprises an arc-shaped first drain electrode and an arc-shaped second drain electrode; the first and second drain electrodes have their mouths facing each other, and are electrically connected to the data line respectively through a branch line; and the gate electrode is a part of a scan line, and is located in an area circled by the first and second drain electrode. 10. The pixel unit according to claim 1 , wherein the drain electrode of a TFT comprises four arc-shaped drain electrode units with their mouths facing outward away from the gate electrode; the drain electrode units are a part of the data line, and are end-to-end connected to enclose an area; and the gate electrode is configured inside the enclosed area, and is part of a scan line. 11. A display device, comprising a plurality of pixel units as claimed in claim 1 arranged in an array.
Interconnections, e.g. scanning lines · CPC title
using masks, e.g. half-tone masks · CPC title
having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title
wherein the TFTs are in active matrices · CPC title
characterised by increasing the uniformity of device parameters · CPC title
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