Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks

Patent metadata

Field	Value
Publication number	US-11322507-B2
Application number	US-202117185709-A
Country	US
Kind code	B2
Filing date	Feb 25, 2021
Priority date	Aug 17, 2020
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a substrate of semiconductor material that includes a first area, a second area and a third area;
recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area;
forming a pair of stack structures in the first area, wherein each of the stack structures includes a floating gate of conductive material disposed over and insulated from the upper surface of the substrate in the first area and a first non-floating gate of conductive material disposed over and insulated from the floating gate;
forming a first source region in the substrate between the pair of stack structures in the first area;
forming a second non-floating gate disposed over and insulated from the first source region in the first area;
forming a block of dummy material disposed over and insulated from the upper surface of the substrate in the third area;
forming third non-floating gates of conductive material disposed over and insulated from the upper surface of the substrate in the first area and each laterally adjacent to and insulated from one of the stack structures;
forming fourth non-floating gates of conductive material disposed over and insulated from the upper surface of the substrate in the second area;
forming first drain regions in the substrate in the first area, each adjacent to one of the third non-floating gates;
forming second source regions in the substrate in the second area, each adjacent to one of the fourth non-floating gates;
forming second drain regions in the substrate in the second area, each adjacent to one of the fourth non-floating gates;
forming a third source region in the substrate in the third area, adjacent to the block of dummy material;
forming a third drain region in the substrate in the third area, adjacent to the block of dummy material;
forming a first blocking layer over at least a portion of one of the fourth non-floating gates in the second area;
forming silicide on the first, second and third drain regions, on the second and third source regions, and on a top surface of the fourth non-floating gates which are not underneath the first blocking layer; and
replacing the block of dummy material with a block of metal material.

2. The method of claim 1 , wherein the forming of the second, third and fourth non-floating gates comprises:
forming a conductive layer disposed over and insulated from the upper surfaces in the first and second areas;
forming a protective insulation layer over the conductive layer in the first and second areas;
etching portions of the protective insulation layer and portions of the conductive layer in the first and second areas to form the third non-floating gates from a first portion of the conductive layer and to form the fourth non-floating gates from a third portion of the conductive layer, wherein a second portion of the conductive layer between the pair of stack structures constitutes the second non-floating gate.

3. The method of claim 2 , further comprising:
performing one or more etches to remove portions of the protective insulation layer over the third and fourth non-floating gates and to remove at least a portion of the first blocking layer in the second area.

4. The method of claim 3 , wherein the forming of the silicide further includes forming silicide on top surfaces of the second and third non-floating gates.

5. The method of claim 2 , further comprising:
forming photo resist over the first, second and third areas;
removing the photo resist from the first and second areas;
after the removing of the photo resist and before the forming of the silicide, removing portions of the protective insulation layer over the second, third and fourth non-floating gates.

6. The method of claim 5 , wherein the forming of the silicide further includes forming silicide on top surfaces of the second and third non-floating gates.

7. The method of claim 2 , further comprising:
forming photo resist over the first, second and third areas;
removing the photo resist from the second area and a portion of the photo resist over the first, second and third non-floating gates;
after the removing of the photo resist and before the forming of the silicide, removing portions of the protective insulation layer over the second, third and fourth non-floating gates.

8. The method of claim 7 , wherein the forming of the silicide further includes forming silicide on top surfaces of the second and third non-floating gates.

9. The method of claim 2 , further comprising:
forming photo resist over the first, second and third areas;
removing the photo resist from the second area and portions of the photo resist over the third non-floating gates;
after the removing of the photo resist and before the forming of the silicide, removing portions of the protective insulation layer over the third and fourth non-floating gates.

10. The method of claim 9 , wherein the forming of the silicide further includes forming silicide on top surfaces of the third non-floating gates.

11. The method of claim 2 , further comprising:
forming photo resist over the first, second and third areas after the forming of the protective insulation layer and before the forming of the first blocking layer;
removing the photo resist from the second area; and
thinning a portion of the protective insulation layer on the fourth non-floating gates.

12. The method of claim 11 , wherein after the forming of the silicide, further comprising:
forming a second blocking layer over the first, second and third areas;
removing portions of the second blocking layer over the first, second and third non-floating gates;
forming silicide on top surfaces of the first, second and third non-floating gates.

13. The method of claim 11 , wherein after the forming of the silicide, further comprising:
forming a second blocking layer over the first, second and third areas;
removing portions of the second blocking layer over the second and third non-floating gates;
forming silicide on top surfaces of the second and third non-floating gates.

14. The method of claim 11 , wherein after the forming of the silicide, further comprising:
forming a second blocking layer over the first, second and third areas;
removing portions of the second blocking layer over the third non-floating gates;
forming silicide on top surfaces of the third non-floating gates.

15. The method of claim 11 , wherein after the forming of the silicide and after the replacing of the block of dummy material with the block of metal material, further comprising:
forming a second blocking layer over the first, second and third areas;
removing portions of the second blocking layer over the first, second and third non-floating gates;
forming silicide on top surfaces of the first, second and third non-floating gates.

16. The method of claim 11 , wherein after the forming of the silicide and after the replacing of the block of dummy material with the block of metal material, further comprising:
forming a second blocking layer over the first, second and third areas;
removing portions of the second blocking layer over the second and third non-floating gates;
forming silicide on top surfaces of the second and third non-floating gates.

17. The method of claim 11 , wherein after the forming of the silicide and after the replacing of the block of dummy material with the block of metal material, further comprising

Assignees

• Silicon Storage Tech Inc

Inventors

• Wang Chunming
• Sun Jack
• Liu Xian
• Xing leo
• Do Nhan
• Yang Andy
• Song guo xiang

Classifications

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title