Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technology

Patent metadata

Field	Value
Publication number	US-11322504-B2
Application number	US-201816021019-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jun 28, 2018
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.

First claim

What is claimed is:

1. A memory array, comprising:
a first dielectric layer over first metal traces, wherein the first metal traces extend along a first direction;
second metal traces on the first dielectric layer, wherein the second metal traces extend along a second direction that is perpendicular to the first direction;
third metal traces on a second dielectric layer, wherein the third metal traces extend along the first direction;
a ferroelectric capacitor positioned in a trench, the trench includes one or more sidewalls and a bottom surface above a first metal trace of the first metal traces, wherein the trench has a depth defined from a top surface of the first metal trace to a top surface of a third metal trace of the third metal traces; and
an insulating sidewall layer, a first electrode layer, a ferroelectric layer, and a second electrode layer disposed in the trench of the ferroelectric capacitor, wherein the trench of the ferroelectric capacitor has a rectangular cylinder shape.

2. The memory array of claim 1 , wherein the first metal traces include pads and lines, and wherein the second and third metal traces are adjacent to the one or more sidewalls of the trench of the ferroelectric capacitor, and wherein the third metal traces extend along the first direction that is perpendicular to the second direction of the second metal traces.

3. The memory array of claim 2 , further comprising a third dielectric layer disposed in between the pads and the lines of the first metal traces.

4. The memory array of claim 3 , further comprising:
a first etch stop layer on the third dielectric layer and the first metal traces; and
a second etch stop layer on the second metal traces.

5. The memory array of claim 2 , wherein the bottom surface of trench of the ferroelectric capacitor is disposed on a top surface of a pad of the first metal traces, and wherein the bottom surface of the trench of the ferroelectric capacitor includes the insulating sidewall layer and the first electrode layer.

6. The memory array of claim 1 , further comprising an insulating layer disposed in the trench of the ferroelectric capacitor and surrounded by the second electrode layer.

7. The memory array of claim 1 , wherein the ferroelectric layer is surrounded by the first electrode layer and the second electrode layer, and wherein the ferroelectric layer includes one or more ferroelectric materials, including hafnium zirconium oxide (HfZrO), silicon-doped (Si-doped) hafnium oxide, germanium-doped (Ge-doped) hafnium oxide, aluminum-doped (Al-doped) hafnium oxide, and yttrium-doped (Y-doped) hafnium oxide.

8. The memory array of claim 1 , further comprising a hardmask layer on a top surface of the second dielectric layer, wherein the hardkmask layer has a trench opening that exposes a top surface of the second electrode layer of the ferroelectric capacitor.

9. The memory array of claim 1 , wherein the first and second electrode layers include one or more conductive materials, including ruthenium, tungsten, copper, aluminum, tantalum nitride, titanium nitride, and any combination thereof, wherein the first electrode layer has one or more conductive materials that are similar or different to one or more conductive materials of the second electrode layer, and wherein the first electrode layer has a thickness that is approximately equal to or different than a thickness of the second electrode layer.

10. The memory array of claim 1 , wherein the first and second electrode layers include one or more conductive materials, including ruthenium, tungsten, copper, aluminum, tantalum nitride, titanium nitride, and any combination thereof, wherein the first electrode layer has one or more conductive materials that are similar or different to one or more conductive materials of the second electrode layer, and wherein the first electrode layer has a thickness that is approximately equal to or different than a thickness of the second electrode layer.

11. A method of forming a memory array, comprising:
disposing a first dielectric layer over first metal traces, wherein the first metal traces extend along a first direction;
disposing second metal traces on the first dielectric layer, wherein the second metal traces extend along a second direction that is perpendicular to the first direction;
disposing third metal traces on a second dielectric layer, wherein the third metal traces extend along the first direction;
forming a trench through the third metal traces, the second dielectric layer, the second metal traces, and the first dielectric layer, wherein the trench includes one or more sidewalls and a bottom surface above a first metal trace of the first metal traces, wherein the trench has a depth defined from a top surface of one of the first metal traces to a top surface of one of the third metal traces, and wherein the trench is self-aligned by the third metal traces and the second metal traces; and
disposing an insulating sidewall layer, a first electrode layer, a ferroelectric layer, and a second electrode layer, respectively, into the trench to form a ferroelectric capacitor, wherein the trench of the ferroelectric capacitor has a rectangular cylinder shape.

12. The method of claim 11 , wherein the first metal traces include pads and lines, and wherein the second and third metal traces are adjacent to the one or more sidewalls of the trench of the ferroelectric capacitor, and wherein the third metal traces extend along the first direction that is perpendicular to the second direction of the second metal traces.

13. The method of claim 12 , further comprising disposing a third dielectric layer in between the pads and the lines of the first metal traces.

14. The method of claim 13 , further comprising:
disposing a first etch stop layer on the third dielectric layer and the first metal traces; and
disposing a second etch stop layer on the second metal traces.

15. The method of claim 12 , wherein the bottom surface of the trench of the ferroelectric capacitor is disposed on a top surface of a pad of the first metal traces, and wherein the bottom surface of the trench of the ferroelectric capacitor includes the insulating sidewall layer and the first electrode layer.

16. The method of claim 11 , further comprising disposing an insulating layer in the trench of the ferroelectric capacitor and surrounded by the second electrode layer.

17. The method of claim 11 , wherein the ferroelectric layer is surrounded by the first electrode layer and the second electrode layer, and wherein the ferroelectric layer includes one or more ferroelectric materials, including HfZrO, Si-doped hafnium oxide, Ge-doped hafnium oxide, Al-doped hafnium oxide, and Y-doped hafnium oxide.

18. The method of claim 11 , further comprising disposing a hardmask layer on a top surface of the second dielectric layer, wherein the hardkmask layer has a trench opening that exposes a top surface of the second electrode layer of the ferroelectric capacitor.

19. The method of claim 11 , wherein the first and second electrode layers include one or more conductive materials, including ruthenium, tungsten, copper, aluminum, tantalum nitride, titanium nitride, and any combination thereof, wherein the first electrode layer has one or more conductive materials that are similar or different to one or more conductive materials of the second electrode layer, and wherein the first electrode layer has a thickness that is approximately equal to or different than a thickness of the second electrode layer.

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Assignees

• Intel Corp

Inventors

• Avci Uygar
• Morris Daniel
• Kim Seiyon
• Wang Yih
• Brain Ruth
• Young Ian

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/076

  in via holes or trenches · CPC title