Integrated circuit including at least one memory cell with an antifuse device

Patent metadata

Field	Value
Publication number	US-11322503-B2
Application number	US-202117141498-A
Country	US
Kind code	B2
Filing date	Jan 5, 2021
Priority date	Aug 31, 2018
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

First claim

The invention claimed is:

1. An integrated circuit, including at least one memory cell, wherein the at least one memory cell comprises:
a state transistor having a control gate electrode, a floating gate electrode and a layer of dielectric material positioned between the control gate electrode and the floating gate electrode; and
wherein the layer of dielectric material includes a first portion having a first thickness and a second portion having a second thickness that is thinner than the first thickness;
said second thickness of the second portion being configured to be broken down in response to an applied voltage at the control gate electrode so that the control gate electrode is electrically connected to the floating gate electrode.

2. The integrated circuit according to claim 1 , wherein the control gate electrode is formed by a first polysilicon layer in contact with a top of the layer of dielectric material and wherein the floating gate electrode is formed by a second polysilicon layer in contact with a bottom of the layer of dielectric material.

3. The integrated circuit according to claim 1 , further including an electrically conductive connecting element including a first end that is electrically coupled to the floating gate electrode and a second, free end that extends to a peripheral edge of the integrated circuit.

4. The integrated circuit according to claim 3 , including a sealing ring including metal tracks and vias extending around the entire periphery of the integrated circuit, the connecting element including a crossing part which crosses said sealing ring, the second end being located between the sealing ring and the peripheral edge.

5. The integrated circuit according to claim 1 , further comprising:
a semiconductor well having a bottom that is delimited by a buried semiconductor region;
an insulated vertical electrode in said semiconductor well extending from the upper face of the semiconductor well down to a region close to the bottom of the semiconductor well;
a heavily n-doped region providing electrical continuity between the insulated vertical electrode and the buried semiconductor layer;
wherein said insulated vertical electrode forms the floating gate electrode.

6. The integrated circuit according to claim 5 , further including an electrically conductive connecting element including a first end that is electrically coupled to the insulated vertical electrode and a second, free end that extends to a peripheral edge of the integrated circuit.

7. The integrated circuit according to claim 6 , including a sealing ring including metal tracks and vias extending around the entire periphery of the integrated circuit, the electrically conductive connecting element including a crossing part which crosses said sealing ring, the second end being located between the sealing ring and the peripheral edge.

8. The integrated circuit according to claim 5 , wherein the layer of dielectric material including the first and second portions extends on the upper face of the semiconductor well.

9. The integrated circuit according to claim 1 , wherein the broken down condition of the second portion of the layer of dielectric material fixes the at least one memory cell to be programmed with a first logic state.

10. The integrated circuit according to claim 9 , wherein the non-broken down condition of the second portion of the layer of dielectric material fixes the at least one memory cell to be programmed with a second logic state opposite the first logic state.

11. The integrated circuit according to claim 1 , wherein the integrated circuit is a component of a chip card.

12. The integrated circuit according to claim 1 , further comprising means for reading said at least one memory cell by:
biasing the control gate electrode of the state transistor; and
reading a drain current of the state transistor, wherein a drain current that is below a threshold is indicative of a non-broken down state and wherein a drain current above said threshold is indicative of a broken down state.

13. A method for programming a memory cell including a state transistor having a control gate electrode, a floating gate electrode and a layer of dielectric material positioned between the control gate electrode and the floating gate electrode, wherein the layer of dielectric material includes a first portion having a first thickness and a second portion having a second thickness that is thinner than the first thickness, the method comprising:
to program a first data state: applying a voltage between the control gate electrode and the floating gate electrode at a sufficient voltage level so as to cause a break down at the second portion of the layer of dielectric material so that the control gate electrode is electrically connected to the floating gate electrode; and
wherein a second data state is provided by presence of the second portion of the layer of dielectric material to insulate the control gate electrode from the floating gate electrode.

14. The method according to claim 13 , wherein the operation of programming said at least one memory cell to the first data state includes:
setting a potential of the floating gate electrode to a first reference potential;
applying a second reference potential to the control gate electrode.

15. The method according to claim 14 , wherein the floating gate electrode is electrically connected via a connecting element to a source of the first reference potential, the method further comprising, after programming said at least one memory cell to the first data state, cutting through said connecting element in such a way that a second end of the connecting element is free.

16. The method according to claim 15 , wherein the connecting element extends outside of an integrated circuit sealing ring, and wherein cutting is performed on the connecting element outside of the integrated circuit sealing ring.

Assignees

• St Microelectronics Rousset

Inventors

• Fornara Pascal
• Marinet Fabrice

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title