Process for making interconnect of group III-V semiconductor device, and group III-V semiconductor device including interconnect made thereby

Patent metadata

Field	Value
Publication number	US-11322398-B2
Application number	US-201916702282-A
Country	US
Kind code	B2
Filing date	Dec 3, 2019
Priority date	Sep 10, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.

First claim

What is claimed is:

1. A process for making an interconnect of a group III-V semiconductor device, comprising the steps of:
a) applying a positive photoresist layer having a first thickness on a conductive part of the group III-V semiconductor device;
b) applying an image-reversible photoresist layer having a second thickness on the positive photoresist layer;
c) subjecting the image-reversible photoresist layer and the positive photoresist layer to patternwise exposure so as to permit each of the image-reversible photoresist layer and the positive photoresist layer to be formed into a first portion which is in a developable form and a second portion which is in a non-developable form, the first portion and the second portion of the image-reversible photoresist layer overlying the first portion and the second portion of the positive photoresist layer, respectively;
d) subjecting the image-reversible photoresist layer to image reversal bake so as to convert the first portion and the second portion of the image-reversible photoresist layer from the developable form and the non-developable form into the non-developable form and the developable form, respectively;
e) subjecting the image-reversible photoresist layer and the positive photoresist layer to flood exposure so as to convert the second portion of the positive photoresist layer from the non-developable form into the developable form;
f) subjecting the image-reversible photoresist layer and the positive photoresist layer to development to remove the second portion in the developable form of each of the image-reversible photoresist layer and the positive photoresist layer so as to permit the image-reversible photoresist layer to be formed with undercut sidewalls bordering an opening that extends downwardly to terminate at the conductive part of the group III-V semiconductor device;
g) depositing a diffusion barrier layer on the conductive part of the group III-V semiconductor device through the opening; and
h) depositing a copper layer on the diffusion barrier layer through the opening to form the interconnect.

2. The process according to claim 1 , further comprising, after step h), removing the image-reversible photoresist layer and the positive photoresist layer.

3. The process according to claim 1 , wherein step a) is implemented by spin coating a positive photoresist on the conductive part of the group III-V semiconductor device at a spin speed ranging from 500 rpm to 4500 rpm for a time period ranging from 5 seconds to 60 seconds.

4. The process according to claim 1 , wherein step b) is implemented by spin coating an image-reversible photoresist on the positive photoresist layer at a spin speed ranging from 500 rpm to 6000 rpm for a time period ranging from 5 seconds to 60 seconds.

5. The process according to claim 1 , wherein the second thickness is smaller than the first thickness.

6. The process according to claim 5 , wherein the first thickness is in a range from 2 μm to 12 μm, and the second thickness is in a range from 1.14 μm to 2.3 μm.

7. The process according to claim 1 , wherein in step c), the patternwise exposure is implemented by subjecting the image-reversible photoresist layer and the positive photoresist layer to exposure to a radiation having a wavelength ranging from 365 nm to 436 nm for a time period ranging from 0.3 second to 2 seconds through a mask ( 400 ).

8. The process according to claim 1 , wherein in step d), the image reversal bake is implemented at a baking temperature ranging from 100° C. to 120° C. for a time period ranging from 90 seconds to 150 seconds.

9. The process according to claim 1 , wherein in step e), the flood exposure is implemented by subjecting the image-reversible photoresist layer and the positive photoresist layer to exposure to a radiation having a wavelength ranging from 365 nm to 436 nm for a time period ranging from 5 seconds to 15 seconds.

10. The process according to claim 1 , wherein in step f), the development is implemented in a developer under stirring for a time period ranging from 1.5 minutes to 5 minutes.

11. The process according to claim 1 , wherein step g) includes the sub-steps of:
g1) sputter depositing a first titanium layer having a thickness ranging from 10 nm to 50 nm on the conductive part of the group III-V semiconductor device;
g2) sputter depositing a tungsten nitride layer having a thickness ranging from 30 nm to 60 nm on the first titanium layer; and
g3) sputter depositing a second titanium layer having a thickness ranging from 10 nm to 50 nm on the tungsten nitride layer.

12. The process according to claim 1 , wherein step h) is implemented using an e-gun evaporation system.

13. The process according to claim 2 , wherein the image-reversible photoresist layer and the positive photoresist layer are removed by a lift-off procedure.

14. A group III-V semiconductor device, comprising:
a substrate;
a conductive part formed on said substrate; and
an interconnect formed on said conductive part and made by the process according to claim 1 .

15. The group III-V semiconductor device according to claim 14 , wherein said interconnect has a thickness of larger than 3 μm and up to 10 μm.

Assignees

• Univ National Chiao Tung

Inventors

• Chang Edward-Yi
• Lin Yueh-Chin
• Tsai Ming-Yen
• Chang Po-Sheng

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/4421

  the principal metal being copper · CPC title