Idealized nonvolatile or persistent storage with structure-dependent spare capacity swapping

Patent metadata

Field	Value
Publication number	US-11321237-B1
Application number	US-202016779906-A
Country	US
Kind code	B1
Filing date	Feb 3, 2020
Priority date	Sep 9, 2014
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

First claim

What is claimed is:

1. A storage drive comprising:
a memory controller having an interface to receive commands and associated addresses from a host; and
nonvolatile memory comprising storage units at a hierarchically-superior level, each storage unit at the hierarchically-superior level comprising a programmably-selected number of one or more dies of the nonvolatile memory and being associated with a respective set of storage units at a hierarchically-inferior level;
wherein the memory controller further comprises a register to store programmable configuration parameters for the storage drive, including first values respective to the storage units at the hierarchically-superior level which determine corresponding host-accessible sets of addresses to be respectively mapped to the storage units at the hierarchically-superior level and the programmably-selected number of the one or more dies of the nonvolatile memory respectively associated with the storage units at the hierarchically-superior level, and second values respective to the storage units at the hierarchically-superior level which determine a number of the storage units at the hierarchically-inferior level in the respective set that is to be held in reserve for corresponding ones of the storage units at the hierarchically-superior level;
wherein the memory controller further comprises circuitry to execute each given one of the commands from the host by
identifying one of the storage units at the hierarchically-superior level dependent on the associated address for the given one of the commands, and
identifying a physical address corresponding to one of the storage units at the hierarchically-inferior level which has been mapped to the corresponding host-accessible set of addresses for the identified one of the storage units at the hierarchically-superior level; and

wherein the memory controller further comprises circuitry to track metadata for respective storage units of the nonvolatile memory and to transmit information to the host based on said metadata, the information indicating an extent to which the respective storage units are unutilized and can continue to receive additional write data without being erased.

2. The storage drive of claim 1 wherein the memory controller comprises circuitry to receive programming from the host and to selectively configure at least one of the first values in response to the host programming.

3. The storage drive of claim 1 wherein the memory controller comprises circuitry to receive programming from the host and to selectively configure at least one of the second values in response to the host programming.

4. The storage drive of claim 1 wherein the memory controller comprises circuitry to receive programming from the host and to selectively configure the first values and the second values respective to each of the storage units at the hierarchically-superior level in response to the host programming.

5. The storage drive of claim 1 wherein each of the storage units at the hierarchically-superior level comprises a virtual device.

6. The storage drive of claim 1 wherein each of the storage units at the hierarchically-superior level comprises mutually-exclusive sets of structures, each of the structures being one of a physical channel and a physical die.

7. The storage drive of claim 1 wherein the memory controller comprises circuitry to perform at least one of wear leveling and garbage collection on an independent basis for each storage unit at the hierarchically-superior level.

8. The storage drive of claim 7 wherein the nonvolatile memory is flash memory, wherein the memory controller is embodied as a flash memory controller integrated circuit, and wherein each of the storage units at the hierarchically-inferior level is an erase unit.

9. The storage drive of claim 1 wherein the memory controller further comprises circuitry to, on an independent basis for each respective set, exchange ones of the storage units at the hierarchically-inferior level held in reserve for the respective set for ones of the storage units at the hierarchically-inferior level which have been mapped to the corresponding host-accessible set of addresses for the respective set.

10. The storage drive of claim 9 wherein the circuitry to exchange is to do so in dependence on at least one register setting respective to a given one of the storage units at the hierarchically-superior level, the at least one register setting defining a host-configurable endurance characteristic for the given one of the storage units at the hierarchically-superior level.

11. The storage drive of claim 1 wherein:
the circuitry to execute each given one of the commands is to identify at least one register entry respective to a given one of the storage units at the hierarchically-superior level that is to be accessed in association with one of the commands; and
the memory controller further comprises address translation circuitry to generate the physical address as a function of the register entry specific to the identified one of the storage units at the hierarchically-superior level.

12. The storage drive of claim 1 wherein the memory controller further comprises circuitry to, in conjunction with an operation in the non-volatile memory affecting a particular physical location:
generate an address corresponding to the particular physical location, in a manner dependent on an address value for one of the storage units at the hierarchically-superior level and exactly one of the storage units at the hierarchically-inferior level in the respective set corresponding to the particular physical location; and
transmit the generated address to the host.

13. The storage drive of claim 12 wherein the circuitry to generate the address is to perform modulo arithmetic upon the address value for the one of the storage units at the hierarchically-superior level corresponding to the particular physical location and an address value for the exactly one of the storage units at the hierarchically-inferior level in the respective set in order to generate the address to be transmitted to the host.

14. The storage drive of claim 1 wherein the circuitry to execute comprises address translation circuitry that is to translate each given associated address differently dependent on one of the storage units at the hierarchically-superior level which is specified by an address field subset of the given associated address, and dependent on at least one register setting respective to the one of the storage units at the hierarchically-superior level which is specified by the address field subset.

15. The storage drive of claim 14 wherein each respective register setting comprises at least one host-configurable address mapping value that is one of:
a number of sequential associated addresses before a channel address is to be changed;
a number of sequential associated addresses before a die address is to be changed;
a number of sequential associated addresses before an erase unit address is to be changed; and
a number of sequential associated addresses before a page address is to be changed.

16. The storage drive of claim 1 wherein the circuitry to execute comprises address translation circuitry that is to translate each associated address differently dependent on an address field subset of the associated address, and dependent on an address translation table respective to the one of the storage units at the hierarchically-superior level corresponding to the address field subset.

17. The storage drive of claim 1 wherein:
the hierarchically-inferio

Assignees

• Radian Memory Systems Inc

Inventors

• Lercari Robert
• Chen Alan
• Jadon Mike
• Robertson Craig
• Kuzmin Andrey V

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F3/064

  Management of blocks · CPC title