All-digital closed loop voltage generator

Patent metadata

Field	Value
Publication number	US-11320888-B2
Application number	US-201816124071-A
Country	US
Kind code	B2
Filing date	Sep 6, 2018
Priority date	Sep 6, 2018
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of power gate transistors coupled to an input power supply rail and an output power supply rail, the plurality of power gate transistors to provide an output power supply on the output power supply rail based on a number of the power gate transistors which are turned on;
a first circuitry coupled to the plurality of power gate transistors, wherein the first circuitry is to increment or decrement a value of a codeword and to turn on or off one or more power gate transistors of the plurality of power gate transistors based on the value of the codeword; and
a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative controller to generate an up or down instruction for the first circuitry according to a digital representation of voltage on the output power supply rail, the all-digital proportional-derivative controller includes an oscillator coupled to the output power supply rail, the oscillator is to generate a first clock which is synchronized by a second clock to generate a synchronized clock, and the second circuitry generates the up or down instruction based on a change in a frequency of the synchronized clock and an error of the frequency of the synchronized clock relative to a reference frequency.

2. The apparatus of claim 1 , wherein the second circuitry comprises a counter to count a number of cycles in the synchronized clock in a clock cycle of the second clock to determine the frequency of the synchronized clock.

3. The apparatus of claim 2 , wherein the second circuitry comprises a clock synchronizer to synchronize the first clock by the second clock_to generate the synchronized clock.

4. The apparatus of claim 1 , wherein the second circuitry comprises a first comparator to compare a current value of the frequency of the synchronized clock with a past value of the synchronized clock to generate an output indicating the change in the frequency of the synchronized clock.

5. The apparatus of claim 4 , wherein the second circuitry comprises a second comparator to compare the frequency of the synchronized clock with a reference frequency, to generate an output indicating the error of the frequency of the synchronized clock relative to the reference frequency.

6. The apparatus of claim 5 , further comprising a logic to generate the up or down instruction according to the outputs of the first and second comparators.

7. The apparatus of claim 1 , wherein:
the first circuitry comprises an up/down shifter;
the up/down shifter is to turn on one or more power gate transistors of the plurality of power gate transistors when the error is less than zero and the change in frequency is less than or equal to zero; and
the up/down shifter is to turn off one or more power gate transistors of the plurality of power gate transistors when the error is greater than zero and the change in frequency is greater than or equal to zero.

8. The apparatus of claim 1 , wherein the plurality of power gate transistors comprises p-type transistors.

9. The apparatus of claim 1 , wherein:
the first circuitry comprises an up/down shifter to increment or decrement the value of the codeword in response to the up or down instruction;
the up/down shifter is to increment the value of the codeword when the error is less than zero and the change in frequency is less than or equal to zero; and
the up/down shifter is to decrement the value of the codeword when the error is greater than zero and the change in frequency is greater than or equal to zero.

10. The apparatus of claim 1 , wherein:
the reference frequency corresponds to the oscillator running at a VRETENTION condition; and
in the VRETENTION condition, a minimum voltage is provided on the output power supply rail that allows circuits and logic gates powered by the output power supply rail to remain operational without losing their state values.

11. An apparatus comprising:
a plurality of devices coupled to an input power supply rail and an output power supply rail, the plurality of devices to provide an output power supply on the output power supply rail;
a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality of devices according to a control signal; and
a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an oscillator coupled to the output power supply rail, the oscillator is to generate a first clock, the first clock is synchronized by a second clock to generate a synchronized clock, the second circuitry is to determine an error in a frequency of the synchronized clock relative to a reference frequency and a change in the frequency of the synchronized clock, and the second circuitry is to generate the control signal to increase, decrease or maintain an output power supply of the plurality of devices based on the error and the change.

12. The apparatus of claim 11 , wherein the second circuitry comprises a counter to determine the frequency of the synchronized clock.

13. The apparatus of claim 12 , wherein the second circuitry comprises a clock synchronizer to synchronize the first clock with the second clock, and to generate the synchronized clock, the counter is to determine the frequency of the first clock via the synchronized clock, and the counter is to receive the second clock.

14. The apparatus of claim 11 , wherein the second circuitry comprises:
a first comparator to compare a past frequency of the synchronized clock to a current frequency of the synchronized clock to generate an output indicating the change in the frequency of the synchronized clock; and
a second comparator to compare a reference frequency with the frequency of the synchronized to generate an output indicating the error.

15. The apparatus of claim 11 , wherein:
the first circuitry comprises an up/down shifter;
the up/down shifter is to turn on one or more devices of the plurality of devices when the error is less than zero and the change in the frequency is less than or equal to zero;
the up/down shifter is to turn off one or more devices of the plurality of devices when the error is greater than zero and the change in the frequency is greater than or equal to zero; and
the up/down shifter is to maintain a number of turned on or off devices of the plurality when the error is greater than zero and the change in the frequency is less than zero, or when the error is less than zero and the change in the frequency is greater than zero.

16. A system comprising:
an up/down shifter coupled to a plurality of power gate transistors, wherein the plurality of power gate transistors are coupled to an input power supply rail and an output power supply rail and are to provide an output power supply on the output power supply rail based on a codeword output by the up/down shifter; and
proportional-derivative controller coupled to the output power supply rail, the proportional-derivative controller is to generate an up or down instruction for the up/down shifter according to a digital representation of voltage on the output power supply rail.

17. The system of claim 16 , wherein voltage on the input power supply rail is adjusted for a power state.

18. The system of claim 16 , wherein the proportional-derivative controller comprises an oscillator coupled to the output power supply rail, a clock synchronizer and a counter, the oscillator is to generate a first clock, the clock synchronizer is to synchronize

Assignees

• Intel Corp

Inventors

• Augustine Charles
• Khellah Muhammad
• Raman Arvind
• Choubal Ashish
• Subramanian Karthik
• Afzal Abdullah
• Merchant Feroze

Classifications

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title