Voltage regulation using local feedback

Patent metadata

Field	Value
Publication number	US-11320849-B2
Application number	US-202017006707-A
Country	US
Kind code	B2
Filing date	Aug 28, 2020
Priority date	Aug 28, 2020
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

First claim

What is claimed is:

1. An apparatus, comprising:
a voltage regulator circuit configured to generate a particular voltage on a regulated power supply node using a voltage level of a feedback node;
a package that includes an integrated circuit, and a package power supply node coupled to the regulated power supply node via a power distribution network, wherein the integrated circuit includes:
a control circuit configured to generate a plurality of non-overlapping selection signals;
a first power switch configured to couple the package power supply node to a first local power supply node; and
a second power switch configured to selectively couple, based on the plurality of non-overlapping selection signals, either the package power supply node or the first local power supply node to the feedback node.

2. The apparatus of claim 1 , wherein the integrated circuit includes a third power switch configured to couple the package power supply node to a second local power supply node, and wherein the second power switch is further configured to selectively couple either the package power supply node, the first local power supply node, or the second local power supply node to the feedback node.

3. The apparatus of claim 2 , wherein the integrated circuit further includes a first processor circuit coupled to the first local power supply node, and a second processor circuit coupled to the second local power supply node.

4. The apparatus of claim 3 , wherein the second power switch is further configured to selectively couple, based on the plurality of non-overlapping selection signals, the package power supply node, the first local power supply node, or the second local power supply node to the feedback node.

5. The apparatus of claim 4 , wherein the control circuit is further configured to generate the plurality of non-overlapping selection signals based on respective power consumptions of the first processor circuit and the second processor circuit.

6. A method, comprising:
coupling a package power supply node to a first local supply node and a second local supply node, wherein a first processor core is coupled to the first local supply node, and wherein a second processor core is coupled to second local supply node;
monitoring respective power consumptions of the first processor core and the second processor core;
coupling, based on the respective power consumptions, the first local supply node to a feedback node for a first time period;
coupling, based on the respective power consumptions, the second local supply node to the feedback node for a second time period different than the first time period; and
generating a particular voltage level on the package power supply node using a voltage level of the feedback node.

7. The method of claim 6 , further comprising, in response to a power gating operation for the first processor core, de-coupling the first local supply node from the feedback node and coupling the package power supply node to the feedback node.

8. The method of claim 7 , further comprising selecting, based on the respective power consumptions of the first processor core and the second processor core, a particular one of the first local supply node and the second local supply node to couple to the feedback node.

9. The method of claim 6 , further comprising, coupling the package power supply node to the feedback node for a third time period different than the first and second time periods.

10. The method of claim 6 , wherein generating the particular voltage level includes comparing the voltage level of the feedback node to a reference voltage level.

11. The method of claim 6 , wherein coupling the first local supply node to the feedback node for the first time period includes closing, for the first time period, a power switch coupled between the first local supply node and the feedback node.

12. An apparatus, comprising:
a substrate including a plurality of traces;
a first package coupled to the substrate, wherein the first package includes a first integrated circuit including a voltage regulator circuit configured to generate a particular voltage level on a power supply node using a voltage level of a feedback node, wherein the power supply node is coupled to a particular trace of the plurality of traces, and the feedback node is coupled to a different trace of the plurality of traces; and
a second package coupled to the substrate, wherein the second package includes a second integrated circuit that includes a plurality of processor cores, wherein the second integrated circuit is configured to:
couple the particular trace to a plurality of local supply nodes, wherein a given one of the plurality of local supply nodes is coupled to the a given one of the plurality of processor cores;
couple a first local supply node of the plurality of local supply nodes to the different trace for a first time period; and
couple a second local supply node of the plurality of local supply nodes to the different trace for a second time period different than the first time period.

13. The apparatus of claim 12 , wherein the second integrated circuit is configured, in response to a power gating operation for a first processor core, to de-couple the first local supply node from the different trace and couple the particular trace to the feedback node.

14. The apparatus of claim 12 , wherein the second integrated circuit is further configured to couple the particular trace to the different trace for a third period of time different than the first and second time periods.

15. The apparatus of claim 12 , wherein a first processor core of the plurality of processor cores is coupled to the first local supply node, and a second processor core of the plurality of processor cores is coupled to a second local power supply node.

16. The apparatus of claim 15 , wherein the second integrated circuit is further configured to determine the first time period and the second time period based on respective power consumptions of the first processor core and the second processor core.

17. The apparatus of claim 12 , wherein the second integrated circuit is further configured to:
generate a plurality of selection signals; and
couple the first local supply node to the different trace using a particular one of the plurality of selection signals.

18. The apparatus of claim 17 , wherein the plurality of selection signals is non-overlapping.

Assignees

• Apple Inc

Inventors

• Searles Shawn
• Zyuban Victor
• Abu-Rahma Mohamed

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• H03K17/223

  in field-effect transistor switches · CPC title