Circuit device, physical quantity measuring device, electronic apparatus, and vehicle

Patent metadata

Field	Value
Publication number	US-11320792-B2
Application number	US-202016974352-A
Country	US
Kind code	B2
Filing date	Aug 6, 2020
Priority date	Aug 7, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

Provided is a circuit device including: a clock signal generation circuit generating a plurality of multi-phase clock signals; a time-to-digital conversion circuit performing a count operation based on an i-th clock signal that corresponds to a multi-phase clock signal, to obtain a count value that corresponds to a time difference between transition timings of a first signal and a second signal, to obtain a first digital value that corresponds to a time difference between transition timings of the first signal and a j-th clock signal that corresponds to a multi-phase clock signal, and to obtain a second digital value that corresponds to a time difference between transition timings of the second signal and a k-th clock signal that corresponds to a multi-phase clock signal; and a processing circuit obtaining a digital value that corresponds to the time difference based on the count value, the first digital value, and the second digital value.

First claim

What is claimed is:

1. A circuit device comprising:
a clock signal generation circuit generating a plurality of multi-phase clock signals that have the same frequency and different phases from each other;
a time-to-digital conversion circuit
performing a count operation based on an i-th clock signal that corresponds to any multi-phase clock signal of the plurality of multi-phase clock signals, to obtain a count value that corresponds to a time difference between a transition timing of a first signal and a transition timing of a second signal, to obtain a first digital value that corresponds to a time difference from the transition timing of the first signal to a transition timing of a j-th clock signal that corresponds to any multi-phase clock signal of the plurality of multi-phase clock signals, and to obtain a second digital value that corresponds to a time difference from the transition timing of the second signal to a transition timing of a k-th clock signal that corresponds to any multi-phase clock signal of the plurality of multi-phase clock signals; and

a processing circuit obtaining a digital value that corresponds to the time difference between the transition timing of the first signal and the transition timing of the second signal based on the count value, the first digital value, and the second digital value.

2. The circuit device according to claim 1 , wherein
the time-to-digital conversion circuit includes
a count circuit that performs a count operation from the transition timing of the first signal to the transition timing of the second signal based on the i-th clock signal, and outputs the count value.

3. The circuit device according to claim 1 , wherein
the clock signal generation circuit includes
a ring-type oscillation circuit that outputs the plurality of multi-phase clock signals from a plurality of intermediate nodes.

4. The circuit device according to claim 3 , wherein
the clock signal generation circuit includes
a PLL circuit in which the ring-type oscillation circuit is provided as a voltage controlled oscillation circuit and that generates the plurality of multi-phase clock signals that are phase-synchronized with a reference clock signal generated using a resonator.

5. The circuit device according to claim 1 , wherein
the time-to-digital conversion circuit includes
an oscillation circuit for the first signal that starts oscillation at the transition timing of the first signal and generates an oscillation clock signal for the first signal,
a j-th oscillation circuit that starts oscillation at the transition timing of the j-th clock signal and generates a j-th oscillation clock signal having a frequency different from a frequency of the oscillation clock signal for the first signal,
a first time-to-digital converter that outputs the first digital value based on the oscillation clock signal for the first signal and the j-th oscillation clock signal,
an oscillation circuit for the second signal that starts oscillation at the transition timing of the second signal and generates an oscillation clock signal for the second signal,
a k-th oscillation circuit that starts oscillation at the transition timing of the k-th clock signal and generates a k-th oscillation clock signal having a frequency different from a frequency of the oscillation clock signal for the second signal, and
a second time-to-digital converter that outputs the second digital value based on the oscillation clock signal for the second signal and the k-th oscillation clock signal.

6. The circuit device according to claim 1 , wherein
the clock signal generation circuit outputs a first clock signal corresponding to a first multi-phase clock signal of the plurality of multi-phase clock signals, a second clock signal corresponding to a second multi-phase clock signal, and a third clock signal corresponding to a third multi-phase clock signal, and
each of the i-th clock signal, the j-th clock signal, and the k-th clock signal is one of the first clock signal, the second clock signal, and the third clock signal.

7. The circuit device according to claim 6 , wherein
the time-to-digital conversion circuit includes
a first counter that performs a count operation from the transition timing of the first signal to the transition timing of the second signal based on the first clock signal and outputs a first count value,
a second counter that performs a count operation from the transition timing of the first signal to the transition timing of the second signal based on the second clock signal and outputs a second count value, and
a third counter that performs a count operation from the transition timing of the first signal to the transition timing of the second signal based on the third clock signal and outputs a third count value, and

the processing circuit uses
any one of the first count value, the second count value, and the third count value as the count value.

8. The circuit device according to claim 7 , wherein
the processing circuit determines
which one of the first count value, the second count value, and the third count value is used as the count value based on signal levels of the plurality of multi-phase clock signals at the transition timing of the first signal.

9. The circuit device according to claim 6 , wherein
the time-to-digital conversion circuit includes
an oscillation circuit for the first signal that starts oscillation at the transition timing of the first signal and generates an oscillation clock signal for the first signal,
a first oscillation circuit that starts oscillation at a transition timing of the first clock signal and generates a first oscillation clock signal having a frequency different from a frequency of the oscillation clock signal for the first signal,
a second oscillation circuit that starts oscillation at a transition timing of the second clock signal and generates a second oscillation clock signal having a frequency different from the frequency of the oscillation clock signal for the first signal,
a third oscillation circuit that starts oscillation at a transition timing of the third clock signal and generates a third oscillation clock signal having a frequency different from the frequency of the oscillation clock signal for the first signal,
a first time-to-digital converter that outputs a first digital value for the first signal based on the oscillation clock signal for the first signal and the first oscillation clock signal,
a second time-to-digital converter that outputs a second digital value for the first signal based on the oscillation clock signal for the first signal and the second oscillation clock signal, and
a third time-to-digital converter that outputs a third digital value for the first signal based on the oscillation clock signal for the first signal and the third oscillation clock signal, and

the processing circuit determines
any one of the first digital value for the first signal, the second digital value for the first signal, and the third digital value for the first signal as the first digital value.

10. The circuit device according to claim 9 , wherein
the processing circuit determines
which one of the first digital value for the first signal, the second digital value for the first signal, and the third digital value for the first signal is used as the first digital value based on signal levels of the plurality of multi-phase clock signals at the transition timing of the first signal.

11. The circuit device according to claim 9 , wherein
the time-to-digital conversion circuit includes
an oscillation circuit for the second signal that starts oscillation at the transition timing of the second signal a

Assignees

• Seiko Epson Corp

Inventors

• Sudo Yasuhiro
• Tsutsumi Akio

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• B60R16/02

  electric {constitutive elements} · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title