Display device, method for forming a pattern and method for manufacturing display device

US11320712B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11320712-B2
Application numberUS-202016905306-A
CountryUS
Kind codeB2
Filing dateJun 18, 2020
Priority dateOct 30, 2019
Publication dateMay 3, 2022
Grant dateMay 3, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 Å to about 300 Å, and a thickness of the main conductive layer is in a range of about 1,000 Å to about 20,000 Å.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a display device, the method comprising: forming a doped silicon layer on an amorphous silicon layer; forming a source metal layer on the doped silicon layer, the source metal layer including a copper-containing layer and a titanium-containing layer on the copper-containing layer; forming a photoresist pattern on the source metal layer; wet-etching the source metal layer by applying the photoresist pattern as a mask to form a preliminary source pattern and a data line; partially removing the photoresist pattern to partially expose an upper surface of the preliminary source pattern and to form a first remaining photoresist pattern; wet-etching the preliminary source pattern by applying the first remaining photoresist pattern as a mask to form a source electrode and a drain electrode and to partially expose an upper surface of the doped silicon layer; partially removing the first remaining photoresist pattern to expose an upper tip of a multi-layered source metal pattern including the source electrode, the drain electrode, and the data line and to form a second remaining photoresist pattern; and dry-etching the multi-layered source metal pattern with an etching gas by applying the second remaining photoresist pattern as a mask to remove the upper tip of the multi-layered source metal pattern, wherein the dry-etching of the multi-layered source metal pattern includes a first dry-etching followed by a second dry-etching, the etching gas includes a fluorine-containing compound and a chlorine-containing compound, and the first dry-etching and the second dry-etching have different flow ratios of the fluorine-containing compound and the chlorine-containing compound. 2. The method of claim 1 , wherein the fluorine-containing compound includes at least one of SF 6 , NF 3 and CF 4 , and the chlorine-containing compound includes at least one of Cl 2 and BCl 3 . 3. The method of claim 1 , wherein the etching gas includes SF 6 and Cl 2 . 4. The method of claim 1 , wherein each of the flow ratios of the fluorine-containing compound and the chlorine-containing compound is in a range of about 1:9 to about 3:7. 5. The method of claim 1 , wherein a flow ratio of the fluorine-containing compound and the chlorine-containing compound is in a range of about 1:9 to about 2:8 when performing the first dry-etching, and a flow ratio of the fluorine-containing compound and the chlorine-containing compound is in a range of about 2:8 to about 3:7 when performing the second dry-etching. 6. The method of claim 1 , wherein the doped silicon layer is partially removed to expose the amorphous silicon layer when dry-etching the multi-layered source metal pattern. 7. The method of claim 1 , wherein the source metal layer includes an adhesion-improving layer including at least one of titanium, molybdenum and tungsten and disposed below the copper-containing layer. 8. The method of claim 7 , wherein the multi-layered source metal pattern has a taper angle in a range of about 70° to about 90°, a thickness of the titanium-containing layer is in a range of about 100 Å to about 300 Å, a thickness of the copper-containing layer is in a range of about 1,000 Å to about 20,000 Å, and a thickness of the adhesion-improving layer is in a range of about 50 Å to about 500 Å. 9. The method of claim 1 , wherein the first dry-etching removes a tip of the titanium-containing layer of the source metal pattern; and the second dry-etching increases a taper angle of the copper-containing layer of the source metal pattern.

Assignees

Inventors

Classifications

  • G02F1/1368Primary

    in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Interconnections, e.g. scanning lines · CPC title

  • Multilayer wirings · CPC title

  • Adhesive materials or arrangements · CPC title

  • Electrodes {(reflective electrodes G02F1/133553)} · CPC title

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Frequently asked questions

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What does patent US11320712B2 cover?
A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/1368. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 03 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).