Voltage detection circuit and power-on reset circuit

Patent metadata

Field	Value
Publication number	US-11316514-B2
Application number	US-202017019865-A
Country	US
Kind code	B2
Filing date	Sep 14, 2020
Priority date	Feb 26, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A voltage detection circuit includes a first transistor and a first resistor connected in series between a power supply voltage node and a reference voltage node, a second transistor and a second resistor connected in series between the power supply voltage node and the reference voltage node, a third transistor and a third resistor connected in series between the power supply voltage node and the reference voltage node, and a signal generator that outputs a signal corresponding to a voltage of a connection node between the third transistor and the third resistor. The second transistor is first turned on among the first to third transistors and a voltage level of the power supply voltage node increases, turning off the third transistor, and then a current flows through the first transistor and the first resistor. When the third transistor is turned on, the signal generator changes a logic of the signal.

First claim

The invention claimed is:

1. A voltage detection circuit comprising:
a first transistor and a first resistor connected in series between a power supply voltage node and a reference voltage node;
a second transistor and a second resistor connected in series between the power supply voltage node and the reference voltage node;
a third transistor and a third resistor connected in series between the power supply voltage node and the reference voltage node;
a signal generator that outputs a signal corresponding to a voltage of a connection node between the third transistor and the third resistor;
a fourth transistor and a fourth resistor connected in series between the power supply voltage node and the reference voltage node; and
a fifth resistor connected in parallel between a drain and a source of the fourth transistor,
wherein:
the fourth transistor forms a current mirror circuit with the first transistor,
a voltage level of the power supply voltage node to turn off the second transistor is adjusted in accordance with a resistance value of the fifth resistor,
the second transistor is first turned on among the first to third transistors when power is on and a voltage level of the power supply voltage node increases, turning off the third transistor, and then a current flowing through the first transistor and the first resistor, to turn off the second transistor and turn on the third transistor, and
the signal generator changes a logic of the signal when the third transistor is turned on.

2. The voltage detection circuit of claim 1 , wherein:
the third transistor is turned on or off according to a voltage of a connection node between the second transistor and the second resistor; and
the second transistor is turned on or off according to a voltage of a connection node between the first transistor and the first resistor.

3. The voltage detection circuit of claim 1 , wherein:
a size of the second transistor is greater than a size of the first transistor and a size of the third transistor; and
the size of the third transistor is greater than the size of the first transistor.

4. The voltage detection circuit of claim 1 , wherein a resistance value of the first resistor is greater than a resistance value of the second resistor and a resistance value of the third resistor.

5. The voltage detection circuit of claim 1 , wherein:
a size of the fourth transistor is the same as the size of the first transistor; and
a resistance value of the fourth resistor is smaller than the resistance value of the first resistor.

6. The voltage detection circuit of claim 1 , wherein
the first to third transistors are p-type MOS transistors; and
the signal generator changes a logic of the signal when the voltage level of the power supply voltage node increases to a predetermined voltage level.

7. The voltage detection circuit of claim 1 , wherein the fourth transistor is a p-type MOS transistor.

8. The voltage detection circuit of claim 1 , wherein:
a gate of the second transistor is connected to a drain of the first transistor;
a gate of the third transistor is connected to a drain of the second transistor; and
the signal generator outputs the signal in accordance with a drain voltage of the third transistor.

9. The voltage detection circuit of claim 1 , further comprising:
a first mask signal generator that generates a first mask signal for a first power supply voltage;
a second mask signal generator that generates a second mask signal for a second power supply voltage that is lower than the first power supply voltage; and
a signal synthesizer that outputs a mask signal obtained by synthesizing the first mask signal and the second mask signal, the signal synthesizer being applied with the first mask signal from the first mask signal generator and the second mask signal from the second mask signal generator,
wherein:
the first mask signal generator comprises a first voltage detector comprising fifth to eighth transistors and sixth to tenth resistors having a connection relationship that is the same as a connection relationship of the first to fourth transistors and the first to fifth resistors, the first power supply voltage being applied to a power supply voltage node of the first mask signal generator; and
the second mask signal generator comprises a second voltage detector comprising ninth to twelfth transistors and eleventh to fifteenth resistors having a connection relationship that is that same as a connection relationship of the first to fourth transistors and the first to fifth resistors, the second power supply voltage being applied to a power supply voltage node of the second mask signal generator.

10. The voltage detection circuit of claim 9 , wherein the signal synthesizer changes a logic of the mask signal when both a logic of the first mask signal and a logic of the second mask signal change.

11. The voltage detection circuit of claim 1 , wherein the fifth resistor is a variable resistor.

12. The voltage detection circuit of claim 1 , wherein:
the gate of the fourth transistor, the source of the fourth transistor and the gate of the first transistor are connected to a common node; and
Vg=VDD×R 4 /(R 4 +R 5 ) is established, where the Vg is a voltage at the common node, VDD is a voltage at the power supply voltage, R 4 is a resistance of the fourth resistor, and R 5 is a resistance of the fifth resistor.

13. A power-on reset circuit comprising:
a first comparator that detects whether a first power supply voltage goes beyond a first threshold voltage;
a second comparator that detects whether a second power supply voltage goes beyond a second threshold voltage;
a first mask signal generator comprising a first voltage detection circuit that generates a first mask signal for the first power supply voltage;
a second mask signal generator comprising a second voltage detection circuit that generates a second mask signal for the second power supply voltage, which is lower than the first power supply voltage; and
a signal synthesizer that outputs a mask signal obtained by synthesizing the first mask signal and the second mask signal; and
a power-on reset signal generator that outputs a power-on reset signal for cancelling a power-on reset state when the first comparator detects that the first power supply voltage goes beyond the first threshold voltage, the second comparator detects that the second power supply voltage goes beyond the second threshold voltage, and the signal synthesizer changes a logic of the mask signal,
the first voltage detection circuit comprising:
a first transistor and a first resistor connected in series between a first power supply voltage node to which the first power supply voltage is applied and a reference voltage node;
a second transistor and a second resistor connected in series between the first power supply voltage node and the reference voltage node;
a third transistor and a third resistor connected in series between the first power supply voltage node and the reference voltage node; and
a first signal generator that outputs a signal corresponding to a voltage of a connection node between the third transistor and the third resistor,
the second voltage detection circuit comprising:
a fourth transistor and a fourth resistor connected in series between a second power supply voltage node to which the second power supply voltage is supplied and a reference voltage node;
a fifth transistor and a fifth resistor connected in series between the second power supply voltage node and the reference voltage node;
a sixth transistor and a sixth resistor connected in series between the second power

Assignees

• Kioxia Corp

Inventors

• Ideno Hiroyuki

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H03K17/223 Primary

  in field-effect transistor switches · CPC title

• H03K17/14

  Modifications for compensating variations of physical values, e.g. of temperature · CPC title

• G01R19/16519

  using FET's · CPC title

• H01L27/0629

  Electricity · mapped topic