Bidirectional variable gain amplification

Patent metadata

Field	Value
Publication number	US-11316489-B2
Application number	US-201916557974-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Aug 30, 2019
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

An apparatus is disclosed for bidirectional variable gain amplification. In an example aspect, an apparatus comprises an antenna element of an antenna array and a wireless transceiver. The wireless transceiver comprises a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode and comprises a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier.

First claim

What is claimed is:

1. An apparatus comprising:
an antenna element of an antenna array; and
a wireless transceiver comprising:
a transmit path coupled to the antenna element;
a receive path coupled to the antenna element; and
a phase shifter disposed in both the transmit path and the receive path, the phase shifter configured to operate in an active mode, the phase shifter comprising:
a first bidirectional variable gain amplifier; and
a second bidirectional variable gain amplifier.

2. The apparatus of claim 1 , wherein the phase shifter is configured, based on being in the active mode, to selectively:
amplify a first signal that propagates through the transmit path using both the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier in a transmit mode; and
amplify a second signal that propagates through the receive path using both the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier in a receive mode.

3. The apparatus of claim 2 , wherein the phase shifter is configured to amplify the first signal and amplify the second signal by a factor that is greater than one.

4. The apparatus of claim 1 , wherein the phase shifter comprises a vector modulator, the vector modulator comprising the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier.

5. The apparatus of claim 1 , wherein the phase shifter comprises a quadrature coupling circuit, the quadrature coupling circuit comprising:
a first quadrature port coupled to the first bidirectional variable gain amplifier; and
a second quadrature port coupled to the second bidirectional variable gain amplifier.

6. The apparatus of claim 5 , wherein the first quadrature port and the second quadrature port are associated with a phase delta of approximately ninety degrees.

7. The apparatus of claim 5 , wherein:
the first bidirectional variable gain amplifier and the first quadrature port are associated with a first in-phase channel of the transmit path and a second in phase channel of the receive path; and
the second bidirectional variable gain amplifier and the second quadrature port are associated with a quadrature channel of the transmit path and a third in phase channel of the receive path.

8. The apparatus of claim 1 , wherein:
the first bidirectional variable gain amplifier comprises a first set of transistors configured to selectively:
operate as a first set of input transistors based on an active transmit configuration; and
operate as a first set of output transistors based on an active receive configuration; and

the second bidirectional variable gain amplifier comprises a second set of transistors configured to selectively:
operate as a second set of input transistors based on the active transmit configuration; and
operate as a second set of output transistors based on the active receive configuration.

9. The apparatus of claim 1 , wherein the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier each comprise different ones of the following:
a first port disposed in both the transmit path and the receive path;
a second port disposed in the transmit path;
a third port disposed in the receive path; and
a T-network coupled to the first port, the second port, and the third port, the T-network comprising:
a common node; and
a first branch circuit coupled between the first port and the common node, the first branch circuit comprising a first set of transistors, the first set of transistors comprising at least one first common-gate amplifier;
a second branch circuit coupled between the second port and the common node, the second branch circuit comprising a second set of transistors, the second set of transistors comprising at least one second common-gate amplifier; and
a third branch circuit coupled between the third port and the common node, the third branch circuit comprising a third set of transistors, the third set of transistors comprising at least one third common-gate amplifier.

10. The apparatus of claim 9 , wherein:
the first branch circuit comprises a first switch, the first switch configured to selectively:
connect a first channel terminal of the first set of transistors to a supply voltage; and
connect the first channel terminal of the first set of transistors to a ground;

the second branch circuit is configured to connect a second channel terminal of the second set of transistors to the supply voltage; and
the third branch circuit comprises a third switch, the third switch configured to selectively:
connect a third channel terminal of the third set of transistors to the supply voltage; and
connect the third channel terminal of the third set of transistors to the ground.

11. The apparatus of claim 10 , wherein:
the first branch circuit comprises a first inductor coupled between the first switch and the first channel terminal of the first set of transistors; and
the third branch circuit comprises a third inductor coupled between the third switch and the third channel terminal of the third set of transistors.

12. The apparatus of claim 10 , wherein:
the first switch is configured to connect the first channel terminal of the first set of transistors to the ground in an active transmit configuration, the active transmit configuration based on the active mode of the phase shifter; and
the third switch is configured to connect the third channel terminal of the third set of transistors to the supply voltage in the active transmit configuration.

13. The apparatus of claim 12 , wherein:
the first set of transistors is configured to:
accept an input voltage at the first port in the active transmit configuration, the input voltage associated with a split transmit signal; and
generate a current based on the input voltage in the active transmit configuration; and

the second set of transistors is configured to generate, based on at least a portion of the current, an output voltage at the second port in the active transmit configuration, the output voltage associated with an amplified split transmit signal.

14. The apparatus of claim 13 , wherein:
the third set of transistors is configured to allocate an amount of the current that flows through the second set of transistors in the active transmit configuration.

15. The apparatus of claim 12 , wherein:
the first switch is configured to connect the first channel terminal of the first set of transistors to the supply voltage in an active receive configuration, the active receive configuration based on the active mode of the phase shifter; and
the third switch is configured to connect the third channel terminal of the third set of transistors to the ground in the active receive configuration.

16. The apparatus of claim 15 , wherein:
the third set of transistors is configured to:
accept an input voltage at the third port in the active receive configuration, the input voltage associated with a split receive signal; and
generate a current based on the input voltage in the active receive configuration; and

the first set of transistors is configured to generate, based on at least a portion of the current, an output voltage at the first port, the output voltage associated with an amplified split receive signal.

17. The apparatus of claim 16 , wherein:
the second set of transistors is configured to allocate an amount of the current that flows through the first set of transistors in the active receive configuration.

18.

Assignees

• Qualcomm Inc

Inventors

• Patel Chirag Dipak
• Yu Xinmin
• Leung Lai Kan

Classifications

• H01Q21/0025

  Modular arrays · CPC title

• H03G3/301 Primary

  the gain being continuously variable · CPC title

• H03K5/026

  with a bidirectional operation · CPC title

• H03F3/45632

  in differential amplifiers with FET transistors as the active amplifying circuit (H03F3/4578 takes precedence) · CPC title

• H03F3/62

  Two-way amplifiers · CPC title