Surge protection power supply clamping circuit, chip and communication terminal

Patent metadata

Field	Value
Publication number	US-11316341-B2
Application number	US-202017138571-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	Jun 30, 2018
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

Disclosed are a surge protection power supply clamping circuit, a chip and a communication terminal. The power supply clamping circuit comprises at least one driving unit and discharging unit; the discharging units are connected to the corresponding driving units respectively, and the driving units are connected to the same time delay unit respectively; the time delay units and the discharging units are connected to a power supply voltage and a ground line respectively. The driving units or the discharging units are sequentially controlled in the power supply voltage wiring direction, so that the sum values of an equivalent conduction resistance and an equivalent metal wiring resistance of respective discharging units are the same, and therefore, the uneven conduction of an NMOS transistor caused by different metal wiring resistances due to different metal wiring lengths of the NMOS transistor of each discharging unit can be counteracted.

First claim

What is claimed is:

1. A surge protection power supply clamping circuit, comprising at least one drive unit and at least one discharge unit, wherein the discharge units are connected to the corresponding drive units respectively, the drive units are connected to a same delay unit, and the delay unit and the discharge units are each connected to a power supply voltage and a ground cable; and
the drive units or the discharge units are sequentially controlled in a wiring direction of the power supply voltage, so that each discharge unit has the same sum of an equivalent conduction resistance and an equivalent metal wiring resistance.

2. The power supply clamping circuit according to claim 1 , wherein
the delay unit comprises a resistor module and a capacitor module, one end of the resistor module is connected to the power supply voltage, the other end of the resistor module is connected to one end of the capacitor module and input ends of the drive units, and the other end of the capacitor module is connected to the ground cable.

3. The power supply clamping circuit according to claim 2 , wherein
when the drive units are sequentially controlled in the wiring direction of the power supply voltage so that each discharge unit has the same sum of the equivalent conduction resistance and the equivalent metal wiring resistance, each drive unit is formed by an odd number of inverters connected in series, an input end of a first inverter is used as the input end of the drive unit, and an output end of a last inverter is used as an output end of the drive unit;
each discharge unit comprises the same quantity of NMOS transistors, the input ends of the drive units are connected to the other end of the resistor module, the output ends of the drive units are connected to gate electrodes of the NMOS transistors of the corresponding discharge units respectively, drain electrodes of the NMOS transistors are connected, to the power supply voltage, and source electrodes of the NMOS transistors are connected to the ground cable, and
sizes of the last inverters in the drive units sequentially increase in the wiring direction of the power supply voltage.

4. The power supply clamping circuit according to claim 2 , wherein
when the discharge units are sequentially controlled in the wiring direction of the power supply voltage so that each discharge unit has the same sum of the equivalent conduction resistance and the equivalent metal wiring resistance, each drive unit is formed by an odd number of inverters of the same size connected in series, an input end of a first inverter is used as the input end of the drive unit, and an output end of a last inverter is used as an output end of the drive unit;
each discharge unit comprises at least one NMOS transistor, the input ends of the drive units are connected to the other end of the resistor module, the output ends of the drive units are connected to gate electrodes of the NMOS transistors of the corresponding discharge units respectively, drain electrodes of the NMOS transistors are connected to the power supply voltage, and source electrodes of the NMOS transistors are connected to the ground cable; and
quantities of the NMOS transistors in the discharge units sequentially decrease in the wiring direction of the power supply voltage.

5. A chip, comprising the power supply clamping circuit according to claim 1 .

6. A surge protection power supply clamping circuit, comprising at least one delay unit, at least one drive unit, and at least one discharge unit, wherein the delay units and the discharge units are each connected to a power supply voltage and a ground cable, the delay units are connected to the corresponding drive units respectively, and the drive units are connected to the corresponding discharge units respectively; and
the delay units are sequentially controlled in a wiring direction of the power supply voltage, so that each discharge unit has the same sum of an equivalent conduction resistance and an equivalent metal wiring resistance.

7. The power supply clamping circuit according to claim 6 , wherein
each delay unit comprises a resistor module and a capacitor module, one end of the resistor module is connected to the power supply voltage, the other end of the resistor module is connected to one end of the capacitor module and an input end of the corresponding drive unit, and the other end of the capacitor module is connected to the ground cable.

8. The power supply clamping circuit according to claim 7 , wherein
the resistor module comprises at least one resistor, and when there are a plurality of resistors, the resistors are connected in series, and
the capacitor module comprises at least one capacitor, and when there are a plurality of capacitors, the capacitors are connected in parallel.

9. The power supply clamping circuit according to claim 8 , wherein
the resistor is replaced with an NMOS transistor or a PMOS transistor that operates in a linear region; and
the capacitor is replaced with a MOS capacitor.

10. The power supply clamping circuit according to claim 7 , wherein
when the delay units are sequentially controlled in the wiring direction of the power supply voltage so that each discharge unit has the same sum of the equivalent conduction resistance and the equivalent metal wiring resistance, each drive unit is formed by an odd number of inverters of the same size connected in series, an input end of a first inverter is used as the input end of the drive unit, and an output end of a last inverter is used as an output end of the drive unit,
each discharge unit comprises the same quantity of NMOS transistors, the input ends of the drive units are connected to the other ends of the resistor modules of the corresponding delay units respectively, the output ends of the drive units are connected to gate electrodes of the NMOS transistors of the corresponding discharge units respectively, drain electrodes of the NMOS transistors are connected to the power supply voltage, and source electrodes of the NMOS transistors are connected to the ground cable; and
equivalent resistances of the resistor modules in the delay units sequentially increase in the wiring direction of the power supply voltage.

11. The power supply clamping circuit according to claim 7 , wherein
when the delay units are sequentially controlled in the wiring direction of the power supply voltage so that each discharge unit has the same sum of the equivalent conduction resistance and the equivalent metal wiring resistance, each drive unit is formed by an odd number of inverters of the same size connected in series, an input end of a first inverter is used as the input end of the drive unit, and an output end of a last inverter is used as an output end of the drive unit,
each discharge unit comprises the same quantity of NMOS transistors, the input ends of the drive units are connected to the other ends of the resistor modules of the corresponding delay units respectively, the output ends of the drive units are connected to gate electrodes of the NMOS transistors of the corresponding discharge units respectively, drain electrodes of the NMOS transistors are connected to the power supply voltage, and source electrodes of the NMOS transistors are connected to the ground cable, and
equivalent capacitances of the capacitor modules in the delay units sequentially increase in the wiring direction of the power supply voltage.

12. The power supply clamping circuit according to claim 7 , wherein
when the delay units are sequentially controlled in the wiring direction of the power supply voltage so that each discharge unit has the same sum of the equivalent conduction

Assignees

• Lin Sheng
• Vanchip Tianjin Tech Co Ltd

Inventors

• Lin Sheng

Classifications

• H10D89/819

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/921 Primary

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H9/041

  using a short-circuiting device · CPC title

• H02H9/025

  Current limitation using field effect transistors · CPC title