Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11315944-B2
Application number	US-201916661291-A
Country	US
Kind code	B2
Filing date	Oct 23, 2019
Priority date	Jun 11, 2019
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a channel structure;
insulating structures surrounding the channel structure and stacked to be spaced apart from each other;
interlayer insulating films surrounding a sidewall of the insulating structures, respectively; and
a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure,
wherein the insulating structures include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure,
wherein the gate electrode extends between the protrusion portions which are adjacent to each other, and
wherein the insulating structures are spaced apart from each other in an area where the gate electrode and the channel structure face each other.

2. The semiconductor device of claim 1 , wherein the insulating structures include sidewalls facing the interlayer insulating films, and
wherein the interlayer insulating films are respectively inserted into grooves defined by the sidewalls and the protrusion portions of the insulating structures.

3. The semiconductor device of claim 1 , wherein the insulating structures comprise:
a first material pattern disposed between each of the interlayer insulating films and the channel structure; and
a second material pattern covering each of the edges of the interlayer insulating films and configured of oxide of the first material pattern.

4. The semiconductor device of claim 3 , wherein the first material pattern includes at least one of a silicon oxynitride film (SiON), a silicon nitride film (SiN), and silicon (Si).

5. The semiconductor device of claim 1 , wherein the gate electrode includes recessed portions in a shape corresponding to the protrusion portions.

6. The semiconductor device of claim 1 , wherein the insulating structures comprise:
a first material pattern disposed between each of the interlayer insulating films and the channel structure;
a second material pattern covering each of the edges of the interlayer insulating films; and
a void disposed between the first material pattern and the second material pattern.

7. The semiconductor device of claim 1 , further comprising:
a memory film extending between the insulating structures and the channel structure and between the gate electrode and the channel structure to surround a sidewall of the channel structure,
wherein the memory film includes a tunnel insulating film, a data storage film, and a blocking insulating film which are stacked on the sidewall of the channel structure.

8. A semiconductor device comprising:
a channel structure;
a memory film including a tunnel insulating film surrounding a sidewall of the channel structure, a data storage film surrounding a sidewall of the tunnel insulating film, and a blocking insulating film surrounding a sidewall of the data storage film;
first material patterns surrounding the memory film and stacked to be spaced apart from each other;
interlayer insulating films surrounding a sidewall of the first material patterns, respectively;
a gate electrode extending from between the interlayer insulating films which are adjacent to each other to between the first material patterns which are adjacent to each other; and
second material patterns disposed between the first material patterns and the gate electrode,
wherein the second material patterns are spaced apart from each other in an area where the gate electrode and the memory layer face each other.

9. The semiconductor device of claim 8 , wherein the first material pattern includes at least one of a silicon oxynitride film (SiON), a silicon nitride film (SiN), and silicon (Si).

10. The semiconductor device of claim 8 , wherein the second material patterns are configured of oxide of the first material patterns.

11. The semiconductor device of claim 8 , wherein the second material patterns include protrusion portions extending between the gate electrode and the interlayer insulating films to cover edges of the interlayer insulating films facing the channel structure.

12. The semiconductor device of claim 11 , wherein the protrusion portions extend from an upper portion of the memory film to between the interlayer insulating films and the gate electrode.

13. The semiconductor device of claim 11 , wherein the gate electrode includes recessed portions in a shape corresponding to the protrusion portions.

14. The semiconductor device of claim 8 , wherein the second material patterns include a porous insulating material.

15. The semiconductor device of claim 14 , wherein the porous insulating material extends between each of the interlayer insulating films and the memory film.

16. The semiconductor device of claim 8 , further comprising:
a void formed between the first and second material patterns which are adjacent to each other.

17. The semiconductor device of claim 16 , wherein the void is disposed between each of the interlayer insulating films and the memory film to be spaced apart from the gate electrode by the second material patterns which are in contact with the interlayer insulating films.

18. A semiconductor device comprising:
a stack of a first and second gate electrodes separated with an interlayer insulating film disposed between the first and second gate electrodes;
a channel structure penetrating through the stack; and
insulating structures, each insulating structure disposed between the interlayer insulating film and the channel structure and including a vertical part and first and second protrusion portions at a first and second ends of the vertical part;
wherein the first and second protrusion portions separate respective recessed portions of the first and second gate electrodes from the channel structure, and
wherein the insulating structures are spaced apart from each other in an area where the gate electrode and the channel structure face each other.

Assignees

• Sk Hynix Inc

Inventors

• Seo Moon Sik
• Choi Gil Bok

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H01L27/11521

  Electricity · mapped topic