Transistor, array substrate and method of manufacturing the same, display device
US-2020286929-A1 · Sep 10, 2020 · US
US11315783B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11315783-B2 |
| Application number | US-201916487552-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 20, 2019 |
| Priority date | Sep 20, 2018 |
| Publication date | Apr 26, 2022 |
| Grant date | Apr 26, 2022 |
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A method of fabricating a display substrate is provided. The method includes forming a conductive layer on a base substrate; and performing a chemical vapor deposition process to form an oxide layer on a side of an exposed surface of the conductive layer away from the base substrate, the exposed surface of the conductive layer including copper, the oxide layer formed to include an oxide of a target element M. The chemical vapor deposition process is performed using a mixture of a first reaction gas including oxygen and a second reaction gas including the target element M, at a reaction temperature in a range of 200 Celsius degrees to 280 Celsius degrees. A mole ratio of oxygen element to the target element M in the mixture of the first reaction gas and the second reaction gas is in a range of 40:1 to 60:1.
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What is claimed is: 1. A method of fabricating a display substrate, comprising: forming a conductive layer on a base substrate; and performing a chemical vapor deposition process to form an oxide layer on a side of an exposed surface of the conductive layer away from the base substrate, the exposed surface of the conductive layer comprising copper, the oxide layer formed to comprise an oxide of a target element M; wherein the chemical vapor deposition process is performed using a mixture of a first reaction gas comprising oxygen and a second reaction gas comprising the target element M, at a reaction temperature in a range of 200 Celsius degrees to 280 Celsius degrees; and a mole ratio of oxygen element to the target element M in the mixture of the first reaction gas and the second reaction gas is greater than 40:1 and less than 50:1. 2. The method of claim 1 , wherein prior to performing the chemical vapor deposition process, the base substrate having the conductive layer is not pre-heated. 3. The method of claim 1 , prior to performing the chemical vapor deposition process, further comprising pre-heating the base substrate having the conductive layer for a duration no more than 5 seconds. 4. The method of claim 1 , wherein the chemical vapor deposition process is performed at a power in a range of 4 kw to 12 kw, and at an atmosphere pressure in a range of 0.7 mtorr to 1.3 mtorr. 5. The method of claim 1 , prior to performing the chemical vapor deposition process, further comprising cleaning the exposed surface of the conductive layer using a protective plasma. 6. The method of claim 5 , wherein cleaning the exposed surface of the conductive layer using the protective plasma is performed for a duration in a range of 5 seconds to 30 seconds. 7. The method of claim 5 , wherein the protective plasma comprises nitrogen, argon, or a combination of nitrogen and argon. 8. The method of claim 5 , wherein a flow of the protective plasma comprises the protective gas is in a range of 30000 sccm to 50000 sccm. 9. The method of claim 1 , wherein the target element M is silicon, and the oxide layer comprises SiO x. , 0<x≤2. 10. The method of claim 1 , wherein the first reaction gas comprises N 2 O, and the second reaction gas comprises SiH 4 . 11. The method of claim 1 , wherein the conductive layer is a layer selected from a group consisting of a gate electrode of a thin film transistor, a gate line, a source electrode of a thin film transistor, a drain electrode of a thin film transistor, a data line, and a common electrode signal line. 12. The method of claim 1 , wherein the conductive layer comprises a gate electrode and a gate line connected to the gate electrode, the gate electrode and the gate line formed in a same layer; and the oxide layer comprises an inter-layer dielectric layer in direct contact with the gate electrode and the gate line. 13. The method of claim 1 , wherein the conductive layer comprises a source electrode, a drain electrode, and a data line connected to the source electrode, the source electrode, the drain electrode, and the data line formed in a same layer; and the oxide layer comprises a protective layer in direct contact with the source electrode, the drain electrode, and the data line. 14. The method of claim 1 , wherein forming the conductive layer comprises forming a first sub-layer and forming a second sub-layer on a side of the first sub-layer away from the base substrate, the exposed surface of the conductive layer being an exposed surface of the second sub-layer; the second sub-layer is formed to comprise copper; and the first sub-layer comprises a Molybdenum-Niobium alloy or a Molybdenum-Titanium alloy. 15. A display substrate fabricated by a method of claim 1 . 16. A display apparatus, comprising the display substrate of claim 15 , and one or more integrated circuits connected to the display substrate.
the material being a silicon oxide, e.g. SiO2 · CPC title
by exposure to a plasma · CPC title
using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title
characterised by the compositions or shapes of the interlayer dielectrics · CPC title
Interconnections, e.g. scanning lines · CPC title
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