Shift register unit and driving method thereof, gate drive circuit and display device

Patent metadata

Field	Value
Publication number	US-11315496-B2
Application number	US-201916472591-A
Country	US
Kind code	B2
Filing date	Jan 14, 2019
Priority date	Jun 6, 2018
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A shift register unit and a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, connected to a pull-up node, and configured to charge the pull-up node according to an input signal; an output circuit, connected to the pull-up node and an output terminal, and configured to output an output signal to the output terminal under control of a voltage of the pull-up node; a reset circuit, connected to the pull-up node, and configured to reset the pull-up node; and a reset signal control circuit, connected to a first reset terminal and the reset circuit, and configured to generate and output a reset control signal according to a reset control input signal and a reset signal provided by the first reset terminal; the reset control signal is configured to control the reset circuit to perform a reset operation.

First claim

What is claimed is:

1. A shift register unit, comprising:
an input circuit, connected to a pull-up node, and configured to charge the pull-up node according to an input signal;
an output circuit, connected to the pull-up node and an output terminal respectively, and configured to output an output signal to the output terminal under control of a voltage of the pull-up node;
a reset circuit, connected to the pull-up node, and configured to reset the pull-up node; and
a reset signal control circuit, connected to a first reset terminal and the reset circuit respectively, and configured to generate and output a reset control signal according to a reset control input signal and a reset signal provided by the first reset terminal,
wherein the reset control signal is configured to control the reset circuit to perform a reset operation the reset signal control circuit is further connected to the output terminal to receive the output signal as the reset control input signal;
the reset signal control circuit is further connected to a total reset terminal, and is further configured to stop outputting the reset control signal according to a total reset signal provided by the total reset terminal;
the reset signal control circuit comprises a reset control input sub-circuit, a reset control output sub-circuit, and reset control reset sub-circuit, the reset control input sub-circuit is connected to a first node, and is configured to charge the first node according to the reset control input signal;
the reset control output sub-circuit is respectively connected to the first reset terminal, the first node and a second node, and is configured to generate and output the reset control signal to the second node according to the reset signal under control of a voltage of the first node;
the reset control reset sub-circuit is connected to the first node and the total reset terminal and is configured to reset the first node under control of the total reset signal provided by the total reset terminal;
the reset signal control circuit further comprises a reset control noise reduction sub-circuit, the reset control noise reduction sub-circuit is connected to the second node and the total reset terminal, and is configured to perform denoising on the second node under control of the total reset signal provided by the total reset terminal;
the reset control input sub-circuit comprises a third transistor, a first terminal of the third transistor is connected to a first preset power supply, a second terminal of the third transistor is connected to the first node, and a control terminal of the third transistor is configured to receive the reset control input signal;
the reset control output sub-circuit comprises a fourth transistor and a second capacitor, a first terminal of the fourth transistor is connected to the first reset terminal, a second terminal of the fourth transistor is connected to the second node, a control terminal of the fourth transistor is connected to the first node, a first terminal of the second capacitor is connected to the first node, and a second terminal of the second capacitor is connected to the second node;
the reset control noise reduction sub-circuit comprises a fifth transistor, a first terminal of the fifth transistor is connected to the second node, a second terminal of the fifth transistor is connected to a second preset power supply, and a control terminal of the fifth transistor is connected to the total reset terminal; and
the reset control reset sub-circuit comprises a sixth transistor, a control terminal of the sixth transistor is connected to the total reset terminal, a first terminal of the sixth transistor is connected to the first node, and a second terminal of the sixth transistor is connected to the second preset power supply.

2. The shift register unit according to claim 1 , wherein the reset circuit is further connected to the output terminal, and is configured to reset the output terminal under control of the reset control signal.

3. The shift register unit according to claim 2 , wherein the reset circuit further comprises an eighth transistor,
a first terminal of the eighth transistor is connected to the output terminal, a control terminal of the eighth transistor is connected to the reset signal control circuit to receive the reset control signal, and a second terminal of the eighth transistor is connected to a third preset power supply.

4. The shift register unit according to claim 1 , further comprising:
a pull-down circuit, connected to the output terminal and the total reset terminal respectively, and configured to reset the output terminal according to the total reset signal provided by the total reset terminal;
a noise control circuit, connected to a second clock signal terminal and a pull-down node respectively, and configured to pull up a voltage of the pull-down node according to a second Clock signal provided by the second clock signal terminal;
a first denoising circuit, connected to the pull-down node and the pull-up node respectively; and configured to perform denoising on the voltage of the pull-up node under control of the voltage of the pull-down node; and
a second denoising circuit, connected to the pull-down node and the output terminal respectively, and configured to perform denoising on the output terminal under control of the voltage of the pull-down node.

5. The shift register unit according to claim 4 , wherein the reset signal is the second clock signal.

6. The shift register unit according to claim 4 , wherein the pull-down circuit comprises a ninth transistor,
a first terminal of the ninth transistor is connected to the output terminal, a control terminal of the ninth transistor is connected to the total reset terminal, and a second terminal of the ninth transistor is connected to a third preset power supply;
the noise control circuit comprises:
a tenth transistor, wherein a first terminal of the tenth transistor is connected to a control terminal of the tenth transistor and then connected to the second clock signal terminal, and a second terminal of the tenth transistor is connected to a third node;
an eleventh transistor, wherein a first terminal of the eleventh transistor is connected to the second clock signal terminal, a control terminal of the eleventh transistor is connected to the third node, and a second terminal of the eleventh transistor is connected to the pull-down node;
a twelfth transistor, wherein a first terminal of the twelfth transistor is connected to the third node, a control terminal of the twelfth transistor is connected to the pull-up node, and a second terminal of the twelfth transistor is connected to a third preset power supply; and
a thirteenth transistor, wherein a first terminal of the thirteenth transistor is connected to the pull-down node, a control terminal of the thirteenth transistor is connected to the pull-up node, and a second terminal of the thirteenth transistor is connected to the third preset power supply.

7. The shift register unit according to claim 4 , wherein the first denoising circuit comprises a fourteenth transistor, the second denoising circuit comprises a fifteenth transistor,
a first terminal of the fourteenth transistor is connected to the pull-up node, a control terminal of the fourteenth transistor is connected to the pull-down node, and a second terminal of the fourteenth transistor is connected to a third preset power supply; and
a first terminal of the fifteenth transistor is connected to the output terminal, a control terminal of the fifteenth transistor is connected to the pull-down node, and a second terminal of the fifteenth transistor is connected to the third preset power supply.

8. The shift register unit according to claim

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xiao Lijun
• Tian Zhenguo
• Zhao Yanan
• Gao Shaohong
• Liu Zhiyou
• Deng Ming

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title