Verification of instructions from main processor to auxiliary processor

Patent metadata

Field	Value
Publication number	US-11314518-B2
Application number	US-201716322983-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Aug 4, 2016
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A method of monitoring execution in an execution environment of an operation, for example a cryptographic operation, comprising a sequence of instructions, is disclosed. Instructions sent in the sequence from a main processor to one or more auxiliary processors, for example cryptographic processors, to execute the operation are monitored and the sequence of instructions is verified using verification information. The method comprises enabling output from the execution environment of a result of the operation in response to a successful verification of the sequence, or generating a verification failure signal in response to a failed verification of the sequence.

First claim

The invention claimed is:

1. A method of securing execution in an execution environment of an operation comprising a sequence of instructions, the method comprising:
monitoring communications between a main processor and one or more auxiliary processors, the communications comprising instructions sent in the sequence on a data bus from the main processor to the one or more auxiliary processors to execute the operation;
verifying the sequence of instructions on the data bus using verification information; and
in response to a successful verification of the sequence of instructions, enabling one of the auxiliary processors to process an instruction of the sequence of instructions; and
in response to a failed verification of the sequence, generating a verification failure signal.

2. The method according to claim 1 , comprising updating a state with each instruction in the sequence, wherein verifying the sequence comprises verifying the state using the verification information.

3. The method according to claim 2 , wherein verifying the state comprises comparing the state with the verification information.

4. The method according to claim 2 , wherein updating the state comprises receiving the sequence of instructions as it is sent from the main processor to the one or more auxiliary processors and updating the state as the sequence of instructions is received.

5. The method according to claim 1 , comprising receiving a request to enable output of a result of the operation and verifying the sequence in response to receiving the request.

6. The method according to claim 5 , wherein the request is received from the main processor.

7. The method according claim 5 , wherein the request comprises the verification information.

8. The method according to claim 1 , wherein the verification information is stored together with code for execution by the main processor to execute the operation.

9. The method according claim 1 , wherein enabling one of the auxiliary processors to process an instruction of the sequence of instructions comprises enabling access by the main processor to the one or more auxiliary processors by using a data switch.

10. A method of preparing code for execution by the main processor to implement an operation in a method as claimed in claim 1 , the method of preparing code for execution by the main processor comprising deriving the verification information from a sequence of instructions for one or more auxiliary processors in the code and including the verification information with the code.

11. A computing device comprising an isolated environment, the isolated environment comprising:
a main processor configured to execute an operation;
one or more auxiliary processors configured to receive instructions from the main processor, execute the instructions and return respective responses to the main processor, wherein executing the operation comprises the main processor sending the instructions and receiving the respective responses;
an interface interfacing between the isolated environment and a remainder of the computing device to receive a result of the operation from the main processor and make it accessible from outside the isolated environment; and
a tracking module configured to:
monitor communications between the main processor and the one or more auxiliary processors, the communications comprising the instructions sent on a data bus from the main processor to the one or more auxiliary processors;
verify a sequence of the instructions on the data bus using verification information; and
in response to a successful verification of the sequence of the instructions to enable one of the auxiliary processors to process an instruction of the sequence of instructions;
in response to a failed verification of the sequence to generate a verification failure signal.

12. The computing device according to claim 11 , wherein the tracking module is configured to implement a method according to claim 2 .

13. The computing device according to claim 11 , wherein the computing device comprises a code memory for storing, together with the verification information, code for execution by the main processor to implement the operation, wherein the code memory is outside the isolated environment.

14. The computing device according to claim 11 , wherein the computing device further comprises at least one data switch and wherein the tracking module controls the at least one data switch to enable or disable access from the main processor to one of the auxiliary processors.

15. The computing device according to claim 11 , wherein the computing device further comprises at least one data switch and wherein the tracking module controls the at least one data switch to enable or disable access from the main processor to the interface.

16. A computer-readable non-transitory storage medium comprising a net list, the net list comprising a specification of circuit elements, and their interconnection, of an isolated environment in accordance with claim 11 .

Assignees

• Nagravision Sa

Inventors

• Macchetti Marco
• Fischer Nicolas
• Perrine Jerome

Classifications

• G06F21/554 Primary

  involving event detection and direct action · CPC title

• G06F21/72

  in cryptographic circuits · CPC title

• G06F9/3877 Primary

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F11/28

  by checking the correct order of processing (G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19) · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title