Tamper resistant counters

Patent metadata

Field	Value
Publication number	US-11310028-B2
Application number	US-201916264416-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Jan 31, 2019
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A method of persistently storing event counts includes generating, using a secret cryptographic key, a sequence of numbers arranged in a pseudorandom order. The sequence of numbers is indicative of a sequence of addresses of cells in an array of cells. Each cell in the array of cells is programmable from an initial state to a programmed state to persistently encode data indicative of counter values associated with a particular event. The method also includes comparing addresses of cells having the programmed state with the sequence of addresses to determine whether a tampering event occurred at the array of cells. The method further includes, based on the determination, authenticating the array of cells or performing a countermeasure.

First claim

What is claimed is:

1. A device for persistently storing event counts, the device comprising:
an array of cells, each cell in the array of cells configured to be programmed from an initial state to a programmed state to persistently encode data indicative of counter values associated with a particular event;
a sequence generator configured to generate, using a secret cryptographic key, a sequence of numbers arranged in a pseudorandom order, the sequence of numbers indicative of a sequence of addresses of cells in the array of cells; and
an event counter module configured to:
compare addresses of cells having the programmed state with the sequence of addresses to determine whether a tampering event occurred at the array of cells based on an order of addresses in the sequence of addresses, wherein the event counter module is configured to determine that the tampering event did not occur in response to a determination that the addresses of cells having the programmed state correspond to a valid counter value indicated by the sequence of addresses, wherein a first valid counter value corresponding to the sequence of addresses is represented by a first set of programmed cells, wherein a second valid counter value corresponding to the sequence of addresses is represented by a second set of programmed cells, wherein the second set of programmed cells includes the first set of programmed cells and a particular set of cells, and wherein the first set of programmed cells does not include the particular set of cells;
based on the determination, authenticate the array of cells or perform a countermeasure; and
responsive to an occurrence of the particular event and authentication of the array of cells as corresponding to the first valid counter value, program the particular set of cells in the array of cells from the initial state to the programmed state, wherein the particular set of cells is identified based on the order of addresses in the sequence of addresses.

2. The device of claim 1 , wherein a third valid counter value corresponding to the sequence of addresses is represented by a third set of programmed cells, wherein the third set of programmed cells includes the second set of programmed cells and a second particular set of cells, wherein the second particular set of cells is identified based on the order of addresses in the sequence of addresses, and wherein the event counter is configured to, responsive to a second occurrence of the particular event and authentication of the array of cells as corresponding to the second valid counter value, program the second particular set of cells in the array of cells from the initial state to the programmed state.

3. The device of claim 1 , wherein the particular set of cells includes at least one cell that has a first particular memory address that is before a second particular memory address of at least one cell of the first set of programmed cells, and wherein a first plurality of memory addresses of the particular set of cells is subsequent to a second plurality of memory addresses of the first set of programmed cells in the sequence of addresses.

4. The device of claim 1 , wherein the event counter module is configured to determine that the tampering event occurred in response to a determination that:
a first particular cell corresponding to a first particular number in the sequence of numbers is in the initial state; and
a second particular cell corresponding to a second particular number in the sequence of numbers is in the programmed state, the second particular number following the first particular number in the sequence of numbers.

5. The device of claim 1 , wherein each cell in the array of cells comprises a one-time programmable memory cell.

6. The device of claim 1 , wherein, in response to a determination that the tampering event failed to occur, the event counter module is further configured to:
identify, in the sequence of numbers, a last particular number that corresponds to a cell in the programmed state, the last particular number associated with a current counter value;
determine a number of cells to be programmed for a next counter value; and
identify particular numbers, in the sequence of numbers, that sequentially follow the last particular number, wherein a quantity of the particular numbers is equal to the number of cells to be programed, wherein the particular numbers correspond to the particular set of cells.

7. The device of claim 1 , wherein, in response to a determination that the tampering event failed to occur, the event counter module is further configured to:
identify, in the sequence of numbers, a last particular number that corresponds to a cell in the programmed state, the last particular number associated with a current counter value;
determine a number of cells to be programmed for a next counter value, wherein the number of cells is pseudo-random and dependent on the secret cryptographic key; and
identify a set of numbers in the sequence of numbers corresponding to the next counter value, a first number in the set of numbers sequentially following the last particular number, and the set of numbers comprising sequential numbers in the sequence of numbers, wherein the set of numbers corresponds to the particular set of cells.

8. The device of claim 7 , wherein a size of the set of numbers is encoded into the sequence of numbers or a second sequence of numbers.

9. The device of claim 8 , wherein the size is pseudorandom and has a value of one, two, three, or four.

10. The device of claim 1 , wherein the particular event is associated with at least one of powering on a flight computer or booting the flight computer.

11. The device of claim 1 , wherein the particular event is associated with an automotive security system.

12. The device of claim 1 , wherein the array of cells, the sequence generator, and the event counter module are integrated on a die, the die further comprising a processor, and wherein the countermeasure comprises at least one of deleting data from an external memory, deleting data from an internal memory, or restricting access to one or more operations of the processor.

13. A method of persistently storing event counts, the method comprising:
generating, using a secret cryptographic key, a sequence of numbers arranged in a pseudorandom order, the sequence of numbers indicative of a sequence of addresses of cells in an array of cells, each cell in the array of cells programmable from an initial state to a programmed state to persistently encode data indicative of counter values associated with a particular event;
comparing addresses of cells having the programmed state with the sequence of addresses to determine whether a tampering event occurred at the array of cells based on an order of addresses in the sequence of addresses,. wherein the tampering event is determined to have not occurred in response to a determination that the addresses of cells having the programmed state correspond to a valid counter value indicated by the sequence of addresses, wherein a first valid counter value corresponding to the sequence of addresses is represented by a first set of programmed cells, wherein a second valid counter value corresponding to the sequence of addresses is represented by a second set of programmed cells, wherein the second set of programmed cells includes the first set of programmed cells and a particular set of cells, and wherein the first set of programmed cells does not include the particular set of cells;
based on the determination:
authenticating the array of cells; or
performing a countermeasure; and

responsive to an occurrence of the particular

Assignees

• Boeing Co

Inventors

• Hars Laszlo

Classifications

• H04L9/0869

  involving random numbers or seeds · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• H04L9/002 Primary

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title