Electrostatic prevention circuit, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11309698-B2
Application number	US-201716073987-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	May 10, 2017
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

An electrostatic prevention circuit, an array substrate and a display device are provided. The electrostatic prevention circuit includes an electrostatic prevention sub-circuit, and the electrostatic prevention sub-circuit includes a thin film transistor and a capacitor; a gate electrode of the thin film transistor is connected to the capacitor, and the thin film transistor is controlled by a signal passing through the capacitor.

First claim

What is claimed is:

1. An electrostatic prevention circuit, comprising: a first thin film transistor and a first capacitor, wherein,
a gate electrode of the first thin film transistor is connected to a first electrode of the first capacitor;
the electrostatic prevention circuit further comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a second capacitor;
a second electrode of the first capacitor is connected to a first electrode of the first thin film transistor, a first electrode of the second thin film transistor and a second electrode of the fourth thin film transistor;
a gate electrode of the third thin film transistor is connected to a first electrode of the second capacitor, and a second electrode of the second capacitor is connected to a first electrode of the third thin film transistor, a first electrode of the fourth thin film transistor and a second electrode of the second thin film transistor;
a gate electrode of the second thin film transistor is connected to a second electrode of the first thin film transistor; and
a gate electrode of the fourth thin film transistor is connected to a second electrode of the third thin film transistor.

2. The electrostatic prevention circuit according to claim 1 , wherein, the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are an N-type MOS thin film transistor.

3. An array substrate, comprising the electrostatic prevention circuit according to claim 1 .

4. The array substrate according to claim 3 , further comprising a first connection structure and a second connection structure, wherein,
a first terminal of the electrostatic prevention circuit and a second terminal of the electrostatic prevention circuit are connected to the first connection structure and the second structure respectively.

5. The array substrate according to claim 4 , wherein, each of the first connection structure and the second connection structure is a signal line or a short-circuit ring.

6. The array substrate according to claim 5 , wherein, the signal line is a gate signal line and or a data signal line, and the short-circuit ring is a gate signal line short-circuit ring or a data signal line short-circuit ring.

7. The array substrate according to claim 3 , wherein,
the array substrate comprises a plurality of the electrostatic prevention circuits and a plurality of connection structures, a first terminal of each of the electrostatic prevention circuits is connected to a same one of the connection structures, and a second terminal of each of the electrostatic prevention circuits is connected to different ones of the connection structures.

8. The array substrate according to claim 7 , wherein, each of the connection structures is a signal line or a short-circuit ring.

9. The array substrate according to claim 8 , wherein, the signal line is a gate signal line or a data signal line, and the short-circuit ring is a gate signal line short-circuit ring or a data signal line short-circuit ring.

10. The array substrate according to claim 3 , wherein,
the array substrate comprises a plurality of the electrostatic prevention circuits, a first connection structure and a second connection structure, a first terminal of each of the electrostatic prevention circuits is connected to the first connection structure, and a second terminal of each of the electrostatic prevention circuits is connected to the second connection structure.

11. A display device, comprising the array substrate according to claim 3 .

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Fang Haobo
• Xue Yanna
• Bao Zhiying
• Zhang Yong
• Mi Lei
• Bai Lu
• Hua Gang
• Wang Jingpeng
• Yuan Lingxiang

Classifications

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• G02F1/136204 Primary

  Arrangements to prevent high voltage or static electricity failures · CPC title