Transistor manufacturing method

Patent metadata

Field	Value
Publication number	US-11309503-B2
Application number	US-201916374805-A
Country	US
Kind code	B2
Filing date	Apr 4, 2019
Priority date	Nov 21, 2013
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A transistor manufacturing method includes forming a source electrode and a drain electrode on a substrate, forming a layer including an insulator layer to cover the source electrode and the drain electrode, and forming a gate electrode on the layer including the insulator layer, wherein the forming the gate electrode includes forming a plating base film, forming a protection layer of the plating base film, forming a photoresist layer on the protection layer to expose the photoresist layer with desired patterning light, causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light, and after depositing a metal on the uncovered plating base film, causing an electroless plating solution to come into contact with the plating base film to perform electroless plating.

First claim

What is claimed is:

1. A transistor manufacturing method comprising:
forming a source electrode and a drain electrode on a substrate;
forming a layer including an insulator layer to cover the source electrode and the drain electrode; and
forming a gate electrode,
wherein the forming the gate electrode comprises
applying a liquid body including a first formation material on at least part of the layer including the insulator layer to form a plating base film;
applying a liquid body including a second formation material on at least part of a surface of the plating base film to form a protection layer of the plating base film;
forming a photoresist layer that includes a photoresist material on a surface of the protection layer to expose the photoresist layer with desired patterning light;
causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light; and
after depositing a metal as a catalyst for electroless plating on a surface of the uncovered plating base film, causing an electroless plating solution to come into contact with the catalyst on the surface of the plating base film to perform electroless plating, and
wherein the transistor manufacturing method comprises exfoliating the protection layer and the photoresist layer after performing the electroless plating.

2. The transistor manufacturing method according to claim 1 , wherein the second formation material is an organic silicon compound having a hydrolysis group that is bonded to a silicon atom.

3. The transistor manufacturing method according to claim 2 , wherein the second formation material is an organic silicon compound having one hydrolysis group that is bonded to the silicon atom.

4. The transistor manufacturing method according to claim 2 , wherein the second formation material is an organic silicon compound having two or three hydrolysis groups that are bonded to the silicon atom.

5. The transistor manufacturing method according to claim 1 , wherein the first formation material is a silane coupling agent that includes a group having at least one of a nitrogen atom and a sulfur atom.

6. The transistor manufacturing method according to claim 5 , wherein the silane coupling agent has an amino group.

7. The transistor manufacturing method according to claim 6 , wherein the silane coupling agent is a primary amine or a secondary amine.

8. The transistor manufacturing method according to claim 1 , wherein the substrate is made of a non-metallic material.

9. The transistor manufacturing method according to claim 8 , wherein the substrate is made of a resin material.

10. The transistor manufacturing method according to claim 9 , wherein the substrate has flexibility.

11. The transistor manufacturing method according to claim 9 , wherein the plating base film is formed by a heat treatment at a heating temperature that is lower than a deformation temperature of the substrate.

12. A transistor manufacturing method comprising:
forming a source electrode and a drain electrode on a substrate;
forming a layer including an insulator layer to cover the source electrode and the drain electrode; and
forming a gate electrode,
wherein the forming the source electrode and the drain electrode on the substrate includes forming at least one of the source electrode and the drain electrode by:
applying a liquid body including a first formation material on at least part of the substrate to form a plating base film;
applying a liquid body including a second formation material on at least part of a surface of the plating base film to form a protection layer of the plating base film;
forming a photoresist layer that includes a photoresist material on an upper surface of the protection layer to expose the photoresist layer with desired patterning light;
causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light; and
after depositing a metal as a catalyst for electroless plating on a surface of the uncovered plating base film, causing an electroless plating solution to come into contact with the catalyst on the surface of the plating base film to perform electroless plating, and
wherein the transistor manufacturing method comprises exfoliating the protection layer and the photoresist layer after performing the electroless plating.

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei
• Sugizaki Takashi
• Kawakami Yusuke

Classifications

• C23C28/00 Primary

  Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D30/6743

  Silicon · CPC title