Vertical gate guard ring for single photon avalanche diode pitch minimization
US-2018026147-A1 · Jan 25, 2018 · US
US11309442B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11309442-B2 |
| Application number | US-201916662713-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 24, 2019 |
| Priority date | Jul 29, 2016 |
| Publication date | Apr 19, 2022 |
| Grant date | Apr 19, 2022 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor substrate has a first surface and a second surface which is opposite to the first surface. A photoelectric conversion portion has a PN junction configured with first and second semiconductor regions of different conductivity types. A buried portion is buried in the semiconductor substrate and includes an electrode and a dielectric member located between the electrode and the semiconductor substrate and in contact with the second semiconductor region. The second semiconductor region is located in a position deeper than the first semiconductor region. The buried portion is located to extend from a first surface to a position deeper than the first semiconductor region. Electric potentials are supplied to the first semiconductor region, the second semiconductor region, and the electrode in such a manner that an inversion layer occurring between the electrode and the second semiconductor region and the first semiconductor region are in contact with each other.
Opening claim text (preview).
What is claimed is: 1. A photodetection device comprising: a substrate having a first surface and a second surface which is opposite to the first surface; a first semiconductor region of a first conductivity type including a majority carrier of a polarity of a signal charge, the first semiconductor region being arranged in a first depth of the substrate; a second semiconductor region of a second conductivity type having different conductivity from the first conductivity type, the second semiconductor region being arranged in a second depth greater than the first depth from the first surface; and a trench structure with polysilicon formed in the substrate from the first surface toward the second surface, the trench structure including a first trench structure portion and a second trench structure portion, wherein the first semiconductor region is arranged between the first trench structure portion and the second trench structure portion in a cross section passing through the first semiconductor region and the second semiconductor region, wherein a semiconductor region of the second conductivity type is arranged between the first trench structure portion and the second surface and between the second trench structure portion and the second surface in the cross section, and wherein a third semiconductor region of the first conductivity type is arranged between an end portion of the first trench structure portion and an end portion of the second trench structure portion. 2. The photodetection device according to claim 1 , wherein a contact plug is arranged at the first surface side and arranged in a region overlapped with the first semiconductor region. 3. The photodetection device according to claim 2 , wherein the polysilicon is a second conductivity doped polysilicon. 4. The photodetection device according to claim 2 , wherein the trench structure is a deep trench isolation. 5. The photodetection device according to claim 2 , wherein the trench structure is arranged to a depth of at least half of a depth of the substrate. 6. The photodetection device according to claim 4 , wherein the polysilicon is buried in the trench structure. 7. The photodetection device according to claim 6 , wherein the first semiconductor region is included in an avalanche diode. 8. The photodetection device according to claim 7 , wherein the first semiconductor region is surrounded by the trench structure in a plan view. 9. The photodetection device according to claim 8 , further comprising a counter circuit which counts a signal of the avalanche diode. 10. The photodetection device according to claim 8 , wherein a fourth semiconductor region of the second conductivity type is arranged between the first semiconductor region and the trench structure. 11. The photodetection device according to claim 10 , wherein the distance between the first semiconductor region and the trench structure is 0.1 μm or less. 12. The photodetection device according to claim 11 , wherein a plurality of the first semiconductor regions are arranged in the substrate in a row direction and a column direction. 13. The photodetection device according to claim 2 , wherein the second semiconductor region is arranged between the first trench structure portion and the second trench structure portion in the cross section. 14. A photodetection system comprising: the photodetection device according to claim 1 ; a light emission unit configured to emit light to be detected by the photodetection device; and a distance calculation unit configured to perform distance calculation using a digital signal stored by the photodetection device. 15. A photodetection system comprising: the photodetection device according to claim 12 ; a light emission unit configured to emit light to be detected by the photodetection device; and a distance calculation unit configured to perform distance calculation using a digital signal stored by the photodetection device. 16. The photodetection device according to claim 1 , wherein the third semiconductor region is arranged between a bottom portion of the first trench structure portion and the second surface.
for devices having potential barriers · CPC title
comprising ring electrodes · CPC title
Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies · CPC title
The active layers comprising only Group IV materials · CPC title
Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.