Thin film transistor and method for manufacturing a thin film transistor

Patent metadata

Field	Value
Publication number	US-11309427-B2
Application number	US-201916642638-A
Country	US
Kind code	B2
Filing date	Mar 4, 2019
Priority date	Mar 4, 2019
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

The present disclosure relates to a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion in source/drain regions of the thin film transistor and located on both sides of the first portion, the second portion and first sub-portions of the first portion adjacent to the second portion include an amorphous semiconductor material, a second sub-portion of the first portion between the first sub-portions includes a polycrystalline semiconductor material, and a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material.

First claim

What is claimed is:

1. A thin film transistor comprising:
a substrate;
a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, wherein the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion located in source/drain regions of the thin film transistor and on both sides of the first portion, wherein the second portion and first sub-portion adjacent to the second portion of the first portion comprise an amorphous semiconductor material, and wherein a second sub-portion, between the first sub-portions, of the first portion comprises a polycrystalline semiconductor material;
a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material, wherein the second semiconductor layer is in contact with a surface of the second portion facing the substrate; and
a source/drain electrode, wherein a surface facing away from the substrate of the second semiconductor layer is in contact with a surface facing towards the substrate of the second portion, and wherein a surface facing towards the substrate of the second semiconductor layer is in contact with a surface facing away from the substrate of the source/drain electrode.

2. The thin film transistor according to claim 1 , wherein a doping type of the first semiconductor layer and a doping type of the second semiconductor layer are an N-type, and wherein an N-type carrier concentration of the second semiconductor layer is greater than an N-type carrier concentration of the first semiconductor layer.

3. The thin film transistor according to claim 1 , wherein a doping type of the first semiconductor layer and a doping type of the second semiconductor layer are a P-type, and wherein a P-type carrier concentration of the second semiconductor layer is greater than a P-type carrier concentration of the first semiconductor layer.

4. The thin film transistor according to claim 1 , wherein a doping concentration of the first semiconductor layer is between 10 17 ions/cm 3 and 10 19 ions/cm 3 , and wherein a doping concentration of the second semiconductor layer is between 10 19 ions/cm 3 and 10 21 ions/cm 3 .

5. The thin film transistor according to claim 1 , wherein the polycrystalline semiconductor material comprises polysilicon, and wherein the amorphous semiconductor material comprises amorphous silicon.

6. A method for manufacturing a thin film transistor, the method comprising:
forming a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially on a substrate, wherein the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion located in a source/drain region of the thin film transistor and on both sides of the first portion, wherein the second portion and first sub-portions, adjacent to the second portion, of the first portion comprise an amorphous semiconductor material, and wherein a second sub-portion, between the first sub-portions, of the first portion comprises a polycrystalline semiconductor material;
forming a second semiconductor layer in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material, wherein the second semiconductor layer is in contact with a surface of the second portion facing the substrate; and
forming a source/drain electrode, wherein a surface facing away from the substrate of the second semiconductor layer is in contact with a surface facing towards the substrate of the second portion, and wherein a surface facing towards the substrate of the second semiconductor layer is in contact with a surface facing away from the substrate of the source/drain electrode.

7. The method for manufacturing a thin film transistor according to claim 6 , wherein forming the first semiconductor layer comprises:
forming a first semiconductor material layer comprising the amorphous semiconductor material, the first semiconductor material layer comprising a middle portion as the first portion and edge portions as the second portion, the edge portions being on both sides of the middle portion; and
converting a portion, corresponding to the second sub-portion, of the middle portion of the first semiconductor material layer into the polycrystalline semiconductor material.

8. The method for manufacturing a thin film transistor according to claim 7 , wherein the converting comprises laser annealing the amorphous semiconductor material.

9. The method for manufacturing a thin film transistor according to claim 8 , wherein the laser annealing comprises using a micro lens array mask.

10. The method for manufacturing a thin film transistor according to claim 6 , wherein forming the first semiconductor layer, the second semiconductor layer, and the source/drain electrode comprises:
forming the source/drain electrode on the substrate;
forming the second semiconductor layer on the source/drain electrode; and
forming the first semiconductor layer on the second semiconductor layer.

11. The method for manufacturing a thin film transistor according to claim 10 , wherein forming the first semiconductor layer and the second semiconductor layer comprises using CVD.

12. The method for manufacturing a thin film transistor according to claim 6 , wherein the polycrystalline semiconductor material comprises polysilicon, and wherein the amorphous semiconductor material comprises amorphous silicon.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zhi
• Yuan Guangcai
• Guan Feng
• Xu Chen
• Wang Xueyong
• Du Jianhua
• Li Chao
• Chen Lei

Classifications

• H10D30/6746

  Amorphous silicon · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/6745 Primary

  Polycrystalline or microcrystalline silicon · CPC title