RRAM voltage compensation

Patent metadata

Field	Value
Publication number	US-11309022-B2
Application number	US-202017135169-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	Jul 16, 2018
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

First claim

What is claimed is:

1. A memory device, comprising:
an array of resistive memory cells;
a plurality of word lines connected to the array of resistive memory cells;
a voltage compensation controller configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines, wherein the voltage compensation controller being configured to determine the word line voltage to be applied to the selected word line of the plurality of word lines comprises the voltage compensation controller being configured to:
determine a segment from a plurality of segments in which the selected word line is located in, and
determine a predetermined word line voltage associated with the determined segment in which the word line is located in as the word line voltage to be applied to the selected word line; and

a word line driver configured to apply the determined word line voltage to the selected word line.

2. The memory device of claim 1 , further comprising an I/O block connected to the array of resistive memory cells.

3. The memory device of claim 2 , wherein the plurality of word lines are segmented into the plurality of segments based a distance of each of the plurality of word lines from the I/O block.

4. The memory device of claim 3 , wherein the plurality of segments comprises a first segment and a second segment, wherein word lines in the first segment are closer to the I/O block than word lines in the second segments.

5. The memory device of claim 4 , wherein a first predetermined word line voltage associated with the first segment is greater than a second predetermined word line voltage associated with the second segment.

6. The memory device of claim 1 , wherein the voltage compensation controller is configured to determine a minimum word line voltage at a first temperature and a maximum word line voltage at a second temperature, the second temperature being higher than the first temperature.

7. The memory device of claim 1 , wherein the array of resistive memory cells includes a first sub array and a second sub array, and wherein the voltage compensation controller is positioned between the first array and the second sub array.

8. A memory device comprising:
an array of resistive memory cells;
a plurality of word lines connected to the array of resistive memory cells;
a voltage compensation controller configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines, wherein the voltage compensation controller being configured to determine the word line voltage to be applied to the selected word line of the plurality of word lines comprises the voltage compensation controller being configured to determine the word line voltage based on a temperature of the array of resistive memory cells, and wherein the voltage compensation controller is configured to determine a minimum word line voltage at a first temperature and a maximum word line voltage at a second temperature, the second temperature being higher than the first temperature; and
a word line driver configured to apply the determined word line voltage to the selected word line.

9. The memory device of claim 8 , wherein the plurality of word lines are segmented into a plurality of segments based a distance of each of the plurality of word lines from an I/O block.

10. The memory device of claim 8 , wherein the word line voltage increases in proportion to the temperature of the array of resistive memory cells from the minimum word line voltage at the first temperature to the maximum word line voltage at the second temperature, the second temperature being higher than the first temperature.

11. The memory device of claim 10 , wherein the word line voltage increases linearly from the minimum word line voltage at the first temperature to the maximum word line voltage at the second temperature, the second temperature being higher than the first temperature.

12. The memory device of claim 8 , wherein the voltage compensation controller includes a temperature compensation circuit configured to receive a temperature of the array of resistive memory cells and output a reference signal, and a location compensation circuit configured to receive the reference signal and determine the word line voltage based on the selected word line and the reference signal.

13. The memory device of claim 8 , wherein the array of resistive memory cells includes a first sub array and a second sub array, and wherein the voltage compensation controller is positioned between the first array and the second sub array.

14. The memory device of claim 8 , further comprising an I/O block connected to the array of memory cells.

15. A method, comprising:
providing an array of resistive memory cells;
providing a plurality of word lines connected to the array of resistive memory cells;
providing an I/O block connected to the plurality of bit lines;
receiving a word line address;
determining a word line voltage for a word line of the plurality of word lines represented by the word line address, wherein determining the word line voltage for the word line of the plurality of word lines represented by the word line address comprises:
determining a segment from a plurality of segments in which the word line is located in, and
determining a predetermined word line voltage associated with the determined segment in which the word line is located in as the word line voltage to be applied to the word line; and

applying the word line voltage to the word line represented by the word line address.

16. The method of claim 15 , further comprising:
segmenting the plurality of word lines of the array of resistive memory cells into the plurality of segments based on a distance of each of the plurality of word lines from the I/O block.

17. The method of claim 16 , further comprising:
associating the predetermined word line voltage to each of the plurality of segments.

18. The method of claim 17 , wherein associating the predetermined word line voltage to each of the plurality of segments comprises:
associating a first predetermined word line voltage to a first segment; and
associating a second predetermined word line voltage to a second segment, wherein the second predetermined voltage level is lower than the first predetermined voltage level, and wherein word lines of the second segment are farther than word lines of the first segment from the I/O block.

19. The method of claim 15 , further comprising:
determining a temperature of the array of resistive memory cells;
determining a temperature compensated word line voltage based on the determined temperature.

20. The method of claim 19 , wherein determining the temperature compensated word line voltage comprises:
determining the temperature compensated word line voltage that increases in proportion to the temperature of the array of resistive memory cells from a minimum word line voltage at a first temperature to a maximum word line voltage at the second temperature higher than the first temperature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chien-An
• Chou Chung-Cheng
• Chih Yu-Der

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0038 Primary

  Power supply circuits · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title