Electronic circuit, particularly for the implementation of neural networks with multiple levels of precision

Patent metadata

Field	Value
Publication number	US-11308388-B2
Application number	US-201615781680-A
Country	US
Kind code	B2
Filing date	Dec 7, 2016
Priority date	Dec 21, 2015
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.

First claim

The invention claimed is:

1. An electronic circuit for the implementation of neural networks, comprising:
a series of calculating blocks that can each implement a group of neurons; and
a transformation block that is linked to said calculating blocks by a communication means and that can be linked at the input of said circuit to an external data bus,
said transformation block transforming the format of the input data and transmitting said data to all or some of said calculating blocks by means of K independent communication channels,
K input data words being each cut up into sub-words such that said sub-words are transmitted over multiple successive communication cycles,
one of said sub-words being transmitted per each of said multiple communication cycles over each of said K communication channels, each being dedicated to one of said input data words, such that said K communication channels can transmit said K input data words in parallel in said multiple communication cycles,
wherein a number of said sub-words, in said respective one input data word, is smaller than a number of bits, in said respective one input data word.

2. The electronic circuit as claimed in claim 1 , wherein said communication means is capable of routing or of broadcasting the data transmitted via said K channels to one or more of said calculating blocks.

3. The electronic circuit as claimed in claim 1 , wherein each calculating block includes at least one calculating module incorporating:
elementary processors in parallel that can each implement the operations of a formal neuron;
a memory storing said data to be sent to said elementary processors, organized into columns each having a width of N bits, N being greater than or equal to 1;
a transformation module that can cut up or join together the sub-words transmitted by said transformation block into other sub-words suitable for the width of said columns; a group of sub-words at the output of said transformation module forming a word, the sub-words of said group being distributed over one or more of said columns according to the coupling mode of said processors to which they are to be sent.

4. The electronic circuit as claimed in claim 3 , wherein the width of said channels is equal to the width of said columns, each channel having a width of N bits.

5. The electronic circuit as claimed in claim 3 , wherein, the granularity of said elementary processors is equal to the width of said columns, said granularity being the maximum number of bits in parallel on any one input of said elementary processors.

6. The electronic circuit as claimed in claim 3 , wherein, in a first coupling mode, a processor being temporally coupled to itself, at least two sub-words which are to be sent thereto are stored in one and the same column so as to be routed to said processor over multiple successive communication cycles.

7. The electronic circuit as claimed in claim 3 , wherein, in a second coupling mode, at least two processors being spatially coupled, the sub-words which are to be sent thereto are stored over multiple columns at one and the same address, said sub-words being routed to said processors in one or more successive communication cycles.

8. The electronic circuit as claimed in claim 5 , wherein the sub-words making up one and the same word can be stored both over multiple addresses and over multiple columns of said memory.

9. The electronic circuit as claimed in claim 3 , further comprising a routing module connected between said memory and said processors, said routing module having a number of inputs that is at least equal to the number of columns, each input being linked to one column only, said routing module being capable of routing the sub-words to said processors.

10. The electronic circuit as claimed in claim 9 , wherein said routing module is capable of broadcasting data from one column to multiple processors.

11. The electronic circuit as claimed in claim 3 , further comprising a memory virtualization block linked to the memories of all of the blocks and to an external memory outside said circuit, via a DMA circuit.

12. A signal processing system for the implementation of neural networks, further comprising a plurality of electronic circuits as claimed in claim 1 .

Assignees

• Commissariat Energie Atomique

Inventors

• Philippe Jean-Marc
• Carbon Alexandre
• Duranton Marc

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/061

  using biological neurons, e.g. biological neurons connected to an integrated circuit · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/08

  Learning methods · CPC title