Securely providing multiple wake-up time options for PCI Express

Patent metadata

Field	Value
Publication number	US-11307638-B2
Application number	US-201816217204-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	Dec 12, 2018
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.

First claim

What is claimed is:

1. A method for effecting changes to the Peripheral Component Interconnect Express (PCIe) L1.2 Substate exit time for a PCIe device having an L1 PM Substates Control 2 Register including a T_POWER_ON Scale field and a T_POWER_ON Value field, comprising:
storing, on the PCIe device, a power mode capability table structure containing information mapping each of a plurality of respective power modes to a T_POWER_ON Scale value and a T_POWER_ON Value value;
generating, at a host coupled to the PCIe device via a PCIe link, a power mode change request defining a power mode;
sending the power mode change request over the PCIe link to the PCIe device;
extracting, at the PCIe device, information identifying the power mode from the power mode change request; and
identifying the T_POWER_ON Scale value and the T_POWER_ON Value value in the power capability table structure corresponding to the power mode that is extracted; and
setting respective values in the T_POWER_ON Scale field and the T_POWER_ON Value field to the T_POWER_ON Scale value and the T_POWER_ON Value value that are identified to change the L1.2 Substate exit time to be used by the PCIe device.

2. The method of claim 1 , further comprising returning a power mode change confirmation from the PCIe device to the host confirming the L1.2 Substate exit time has been changed.

3. The method of claim 2 , wherein each of the power mode change request and the power mode change confirmation comprises a Vender Defined Message (VDM).

4. The method of claim 1 , wherein each of the power mode change request and the power mode change confirmation comprises a Vender-Specific Extended Capability (VSEC) structure.

5. The method of claim 2 , further comprising:
generating, at the PCIe device, a power mode change request response and sending the power mode change request response from the PCIe device over the PCIe link to the host;
processing, at a host application layer on the host, the power mode change request response; and
sending information to a system power management unit that the change of the power mode of the PCIe device has been completed.

6. The method of claim 1 , further comprising:
prior to generating and sending the power mode change request,
obtaining power mode device capability information from the power mode capability table structure of the PCIe device; and
using the power mode device capability information to select the power mode in the power mode change request.

7. The method of claim 6 , further comprising:
sending a first Vendor Defined Message (VDM) comprising a power mode capability read request from the host to the PCIe device via the PCIe link;
reading the power mode capability table structure and generating power mode capability information;
returning the power mode capability information in a second VDM comprising a power mode capability read response sent from the PCIe device via the PCIe link to the host; and
creating or updating a copy of the power mode capability table structure on the host.

8. The method of claim 6 , further comprising:
sending a first Vender-Specific Extended Capability (VSEC) structure comprising a power mode capability read request from the host to the PCIe device via the PCIe link;
reading the power mode capability table structure and generating power mode capability information;
returning the power mode capability information in a second (VSEC) structure comprising a power mode capability read response sent from the PCIe device via the PCIe link to the host; and
creating or updating a copy of the power mode capability table structure on the host.

9. A system comprising:
a host computer, including,
a System on a Chip (SoC) processor having a memory controller and a Peripheral Component Interconnect Express (PCIe) root controller including at least one PCIe root port;
system memory, operatively coupled to the memory controller; and
instructions, to execute on the SoC processor;

a PCIe device, including,
a PCIe port coupled to a PCIe root port via a PCIe link having a L1 PM Substates Control 2 Register including a T_POWER_ON Scale field and a T_POWER_ON Value field;
a power mode capability table structure containing information mapping each of a plurality of respective power modes to a T_POWER_ON Scale value and a T_POWER_ON Value value; and
embedded logic;

wherein execution of the instructions on the SoC processor and the embedded logic respectively enable the host computer and the PCIe device to,
generate, at the host computer, a power mode change request defining a power mode;
send the power mode change request from the host computer over the PCIe link to the PCIe device;
extract, at the PCIe device, information identifying the power mode from the power mode change request;
retrieve a T_POWER_ON Scale value and a T_POWER_ON Value value in the power capability table structure for the power mode that is identified; and
set respective values in the T_POWER_ON Scale field and the T_POWER_ON Value field to the T_POWER_ON Scale value and the T_POWER_ON Value value that are retrieved to change the L1.2 Substate exit time to be used by the PCIe device.

10. The system of claim 9 , wherein the power mode change request comprises a Vender Defined Message (VDM).

11. The system of claim 9 , wherein the power mode change requests comprises a Vender-Specific Extended Capability (VSEC) structure.

12. The system of claim 9 , wherein execution of the instructions on the SoC processor implement a host application layer that is used to generate the power mode change request, wherein the embedded logic on the PCIe device is configured to implement a device application layer, and wherein the information identifying the power mode is extracted from the power mode change request by the device application layer.

13. The system of claim 9 , wherein the host computer further includes a system power management unit either implemented in the SoC processor or coupled to the SoC processor, and wherein execution of the instructions on the SoC processor and the embedded logic respectively enable the host computer and the PCIe device to:
implement a host application layer on the host computer;
generate, at the PCIe device, a power mode change request response;
send the power mode change request response from the PCIe device over the PCIe link to the host computer;
process, at the host application layer, the power mode change request response; and
send information to the system power management unit that the power mode change request has been completed.

14. The system of claim 9 , wherein execution of the instructions on the SoC processor and the embedded logic respectively enable the host computer and the PCIe device to:
prior to generating and sending the power mode change request,
obtain power mode device capability information from the PCIe device defining power modes supported by the PCIe device; and
use the power mode device capability information to select the power mode in the power mode change request.

15. The system of claim 9 , wherein execution of the instructions on the SoC processor and the embedded logic respectively enable the host computer and the PCIe device to: send a first Vendor Defined Message (VDM) comprising a power mode capability read request from the host to the PCIe device via the PCIe link; retrieve power mode capability information from the power mode capability table structure; return the power mode capability information in a second VDM comprising a power mode capability read response sent from the PCIe device via the PCIe link to the host; and c

Assignees

• Intel Corp

Inventors

• Li Ang
• Tan Kuan Hau
• Ooi Eng Hun

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3215

  Monitoring of peripheral devices · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title